Semiconductor memory with built-in cache

ABSTRACT

A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a semiconductor memory device such as adynamic random-access memory (DRAM), more particularly to asemiconductor memory device with a built-in cache in which data can bestored for quick recall.

[0002] A DRAM has, among other circuits, an array of memory cellsidentified by row and column addresses, and a row of sense amplifiers.In read or write access, a row address is input, the memory cells in theaddressed row are coupled to the sense amplifiers, and their data areamplified. Next a column address is input, and in read access forexample, the amplified data for the addressed column are output to adata bus. Further column addresses may then be input to access the dataof other columns in the same row. When such access ends, in aconventional DRAM, the sense amplifiers are disabled, and the dataremain held only in the memory cell array.

[0003] A problem in the conventional DRAM is that before each accesscycle, the sense amplifiers, and the bit lines that couple them to thememory cells, must be precharged by equalizing them to a certainpotential. Furthermore, at the beginning of every cycle, the senseamplifiers must amplify the data in an entire row of memory cells.Substantial time is required for these operations, particularly in alarge-scale memory with long bit lines, which have large intrinsiccapacitances that must be charged and discharged. This severely limitsthe access speed of the device.

[0004] One possible solution to this problem is to retain data in thesense amplifiers by leaving them enabled at the end of an access cycle,thereby using the sense amplifiers as a cache. Then if the same rowaddress is input again, the addressed data are immediately availablefrom the sense amplifiers and do not have to be read from the memorycells. This scheme is particularly suited to a device in which thememory cell array is divided into multiple banks, and multiple rows ofsense amplifiers are provided, permitting data from different banks tobe cached in different sense amplifier rows.

[0005] The utility of this method is restricted, however, by the need torefresh data in DRAM memory cells periodically. Each time a refresh iscarried out, the data being held in the relevant sense amplifiers arelost. The data are also lost if the device is placed in standby and thesense amplifiers are powered down.

[0006] Another problem is that each row of sense amplifiers can holddata for only a single row of memory cells. If access alternates betweentwo rows in the same bank, for example, the above method confers nobenefit.

SUMMARY OF THE INVENTION

[0007] It is accordingly an object of the present invention to enablerapid access to data in a semiconductor memory device.

[0008] Another object of the invention is to avoid loss of rapidlyaccessible data when a refresh occurs.

[0009] Yet another object is to enable refresh cycles and access cyclesto take place simultaneously.

[0010] Still another object is to reduce current dissipation when dataare transferred from memory cells to sense amplifiers.

[0011] The invented semiconductor memory device has a row-column arrayof memory cells for storing data. Bit lines extending in the columndirection transport data to and from memory cells selected by word linesextending in the row direction. The bit lines are coupled via a row offirst switching elements to corresponding sense lines, to which senseamplifiers are coupled.

[0012] According to a first aspect of the invention, one or more rows ofcache cells are coupled to the sense lines. According to a second aspectof the invention, column data lines are coupled via second switchingelements to the sense lines, and one or more rows of cache cells arecoupled to the column data lines.

[0013] In either aspect of the invention, each row of cache cells canstore data from an arbitrary row of memory cells. Data transferred fromthe memory cells to the sense lines and amplified by the senseamplifiers can be placed in the cache cells for quick recall later. Thecache cells can continue to store such data while the sense amplifiersare refreshing the memory cells.

[0014] If the cache cells are coupled to column data lines, then duringrefresh operations, the column data lines can be disconnected from thesense lines, and access to data on the column data lines can continuewhile the refresh is in progress.

[0015] A tag circuit is provided to keep track of the row addresses ofthe memory cells having data stored in the cache cells, and controltransfers of data to and from the cache cells.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a block diagram of a novel DRAM with a cache.

[0017]FIG. 2 is a circuit diagram of a cache cell.

[0018]FIG. 3 is a circuit diagram of another cache cell.

[0019]FIG. 4 is a timing diagram illustrating the operation of the DRAMin FIG. 1.

[0020]FIG. 5 is a block diagram of a DRAM with two cache rows per row ofsense amplifiers.

[0021]FIG. 6 is a timing diagram illustrating the operation of the DRAMin FIG. 5.

[0022]FIG. 7 is a block diagram of a DRAM with four cache rows per rowof sense amplifiers.

[0023]FIG. 8 is a block diagram of a DRAM with a novel circuit forequalizing the sense lines and sense amplifiers.

[0024]FIG. 9 is a timing diagram illustrating the operation of thecircuit in FIG. 8.

[0025]FIG. 10 is a block diagram of a DRAM with another novel circuitfor equalizing the sense lines and sense amplifiers.

[0026]FIG. 11 is a circuit diagram of the hit/miss detector in FIG. 10.

[0027]FIG. 12 is a timing diagram illustrating the operation of thecircuit in FIG. 10.

[0028]FIG. 13 is another timing diagram illustrating the operation ofthe circuit in FIG. 10.

[0029]FIG. 14 illustrates a DRAM having column switching circuits withinternal cache cells.

[0030]FIG. 15 is a timing diagram illustrating the operation of the DRAMin FIG. 14.

[0031]FIG. 16 is another timing diagram illustrating the operation ofthe DRAM in FIG. 14.

[0032]FIG. 17 illustrates a DRAM having write buffers, as well as columnswitching circuits with internal cache cells.

[0033]FIG. 18 is a timing diagram illustrating the operation of the DRAMin FIG. 17.

[0034]FIG. 19 is a timing diagram illustrating two types of refreshoperations in the DRAM of FIG. 17.

[0035]FIG. 20 illustrates a circuit for controlling the coupling of bitlines to sense lines.

[0036]FIG. 21 illustrates a refresh control circuit.

[0037]FIG. 22 illustrates a three-level driver circuit.

[0038]FIG. 23 illustrates a preferred layout of the column switchingcircuits in the DRAM of FIGS. 14 or 17.

[0039]FIG. 24 illustrates another preferred layout of the columnswitching circuits in the DRAM of FIGS. 14 or 17.

[0040]FIG. 25 illustrates a DRAM with rows of sense amplifiers disposedon both sides of a memory cell array.

[0041]FIG. 26 illustrates a preferred layout of the column switchingcircuits in the DRAM of FIG. 25.

DETAILED DESCRIPTION OF THE INVENTION

[0042] Several embodiments of the invention will now be described withreference to the attached illustrative drawings. The drawings have beensomewhat simplified, to avoid obscuring the invention with irrelevantdetail. Control signal lines will be designated by the names of thecontrol signals they carry. All control signals are shown as activehigh, and the high (active) level is denoted by Vcc. The low (inactive)level is denoted by Vss, or by the conventional ground symbol. Somesignals may be boosted to an active level higher than Vcc, as will beexplained later.

[0043] The terms row and column will be used frequently. In thedrawings, rows are vertical and columns are horizontal. In thespecification and claims, the term row will often be used to denote aplurality of identical objects aligned in the row direction. Forexample, a “row of cache cells” describes a row of possibly thousands ofcache cells extending in the vertical direction in the drawings, eventhough only one cache cell in the row is actually shown.

[0044]FIG. 1 is a block diagram of a DRAM provided with a novel cachethat shadows the data held in the sense amplifiers, so that these dataneed not be lost in a refresh or standby.

[0045] The DRAM comprises a memory cell array 2 having memory cells 4coupled to word lines WL1, WL2, . . . which run in the row direction.They are intersected by pairs of complementary bit lines BLi and{overscore (BL)}i running in the column direction. Each memory cell 4 iscoupled to one word line and one bit line. Each pair of complementarybit lines forms one column in the array, BLi and {overscore (BL)}i beingthe bit lines of the i-th column. The bit lines transport data(electrical charges) to and from the memory cells. The word linescontrol the transfer of data between their coupled memory cells and thebit lines.

[0046] Each column has an equalizing circuit 6 coupled between its pairof complementary bit lines BLi and {overscore (BLi)}. These equalizingcircuits are all controlled by a common signal line EQB.

[0047] The memory cell array 2 has word lines, bit lines, and memorycells other than the ones shown in FIG. 1, but they have been omitted tosimplify the drawing.

[0048] The bit lines BLi and {overscore (BL)}i are coupled through atransfer circuit 8 to corresponding pairs of complementary sense linesSi and {overscore (S)}i. The transfer circuit 8 comprises switchingelements such as N-channel metal-oxide-semiconductor transistors (NMOStransistors) 9 controlled by a transfer gate signal TG. Each NMOStransistor 9 is coupled in series between one bit line and thecorresponding sense line, and the gates of all these NMOS transistors 9are coupled in common to the TG control signal line.

[0049] Coupled to the sense lines Si and {overscore (S)}i are a cache 10comprising a row of cache cells 12 for temporarily storing data havingan arbitrary row address, a sense amplifier row 14 comprising a row ofsense amplifiers 16 and a row of sense-line equalizing circuits 18, anda plurality of column switching circuits 20. As illustrated, there isone cache cell 12, sense amplifier 16, sense-line equalizing circuit 18,and column switching circuit 20 per column in the memory cell array 2.The column switching circuit 20 selectively couples the sense lines Siand {overscore (S)}i to a data bus 21 comprising complementary read datalines RDB and {overscore (RDB)} for output of read data, andcomplementary write data lines WDB and {overscore (WDB)} for input ofwrite data.

[0050] Each cache cell 12 is coupled to at least one of the two senselines Si and {overscore (S)}i in its column, and all the cache cells 12are coupled to a common control line that carries a cache control signalSWc. Each sense amplifier 16 is coupled to both sense lines Si and{overscore (S)}i in its column, and all the sense amplifiers 16 arecoupled to a common control line that carries a sense amplifier enablesignal SAE. Each equalizing circuit 18 is coupled to both sense lines Siand {overscore (S)}i in its column, and all the equalizing circuits arecoupled to a common control line EQS.

[0051] The cache 10, sense amplifier row 14, and column switchingcircuits 20 need not be coupled to the sense lines Si and {overscore(S)}i in the order shown in FIG. 1. Another possible order will beillustrated in later embodiments. Furthermore, although the sense linesSi and {overscore (S)}i are shown in the drawings as single lines, it ispossible for the sense amplifiers 16 to have nodes which are coupled byseparate signal lines to the transfer circuit 8, cache cells 12, andcolumn switching circuit 20; the term “sense lines” then encompassesboth these nodes and the separate signal lines connected to them.

[0052] An address buffer 22 is provided for input of row and columnaddresses. An address multiplexer 24 sends the row addresses to acontrol circuit 26. The control circuit 26 has a tag circuit 28 forstoring the row address of the data currently held in the cache 10, anda flag indicating whether the cache contents are valid. When the cachecontents are flagged as invalid, the cache is said to be empty.

[0053] The tag circuit 28 activates a control signal SW when a cache hitoccurs, i.e. when the flag indicates that the cache contents are validand the address stored in the tag circuit 28 matches the current inputrow address. Control signal SW is used in generating the SWc signal thatcontrols the cache 10. The control circuit 26 also has registers (notshown) for holding the current and preceding row address inputs, andvarious logic and timing circuits that generate control signals EQB, TG,and SAE.

[0054] The control circuit 26 furnishes row addresses as appropriate toa row decoder 30, which activates drivers (not shown) to drive thecorresponding word lines in the memory cell array 2. The addressmultiplexer 24 sends column addresses to a column decoder 32, whichcontrols the column switching circuits 20. For the i-th column, thecolumn decoder generates a read column signal RCLi and a write columnsignal WCLi.

[0055] The SW signal output by the control circuit 26 becomes one inputof a two-input NAND gate 34. The other input to this NAND gate 34 is aREF signal that is activated during refresh cycles. The REF signal isgenerated by another control circuit, not shown in the drawing, and isinverted by an inverter 35 before input to the NAND gate 34. The outputof the NAND gate 34 is inverted by another inverter 36 to generate thecache control signal SWc.

[0056] The SAE signal output by the control circuit 26 is inverted by aninverter 38 to generate the EQS signal that controls the equalizingcircuits 18 in the sense amplifier row 14. Additional circuit elements(not shown) are used to provide timing delays between EQS and SAE.

[0057]FIG. 2 shows one preferred configuration of the cache cells 12.The cache cell 12 in this drawing comprises a single switching elementsuch as an NMOS transistor 40, and a storage element such as a capacitor42. The transistor 40 is coupled in series between a sense line Si andone electrode of the capacitor 42. The other electrode of the capacitor42 is coupled to an HVcc line (not shown in FIG. 1) which is held at afixed potential intermediate between the two fixed potential levels Vccand Vss. (Typically, HVcc is halfway between Vcc and Vss.)

[0058] The cache cell configuration in FIG. 2 is similar to theconfiguration of the memory cells 4 in the memory cell array 2. In thepresent embodiment, however, the transistor 40 and capacitor 42preferably have larger dimensions than the corresponding transistors andcapacitors of the memory cells 4, so that the cache can be accessedquickly and does not require frequent refreshing.

[0059]FIG. 3 shows another preferred cache-cell configuration, havingtwo NMOS transistors 40 and 44 coupled in series between complementarysense lines Si and {overscore (S)}i. The gates of both transistors 40and 44 are driven by the cache control line SWc. The capacitor 42 iscoupled in series between the two transistors 40 and 44. This cache celltakes up more space, but has the advantage of faster read-out than thecache cell in FIG. 2, because it creates a greater potential swingbetween the two sense lines Si and {overscore (S)}i.

[0060] Detailed descriptions of the other circuits in FIG. 1 will beomitted at this point, as these circuits will be familiar to thoseskilled in the semiconductor memory art, but the functions of theircontrol signals will be briefly explained.

[0061] When EQB is active, the equalizing circuit 6 equalizes the bitlines BLi and {overscore (BL)}i to the intermediate potential HVcc.

[0062] When TG is active, the transfer circuit 8 couples the bit linesBLi and {overscore (BL)}i to the sense lines Si and {overscore (S)}i.

[0063] When SWc is active, the storage elements in the cache cells 12are coupled to the sense lines Si and {overscore (S)}i, permitting datatransfer. This occurs when SW is active and REF is inactive.

[0064] When SAE is inactive and EQS is active, the sense amplifiers aredisabled, meaning that their Vcc and Vss power supplies (not shown) areswitched off, and the sense lines Si and {overscore (S)}i are equalizedto HVcc. When SAE is active and EQS is inactive, the sense amplifiers 16are enabled, meaning that they are supplied with Vcc and Vss, and if apotential difference exists on the sense lines Si and {overscore (S)}i,they amplify it by pulling the higher sense line up to Vcc and the lowersense line down to Vss.

[0065] When RCLi is active, the column switching circuit couples senselines Si and {overscore (S)}i to the read data lines RDB and {overscore(RDB)}. The coupling may be effected through a simple and well-knowntransistor amplifier circuit, which will be illustrated later. When WCLiis active, sense lines Si and {overscore (S)}i are coupled to the writedata lines WDB and {overscore (WDB)}.

[0066]FIG. 4 is a timing diagram of the DRAM in FIG. 1, showing severaltypes of memory access cycles. For simplicity, it will be assumed thatall accesses are read accesses.

[0067] At the extreme left of FIG. 4, the DRAM is in the standby state:a state in which the sense amplifiers are disabled because no access isoccurring. All word lines are inactive, control signals TG, SW, SWc, andSAE are inactive, and EQB and EQS are active. The bit lines BLi and{overscore (BL)}i and sense lines Si and {overscore (S)}i are equalizedto the intermediate potential HVcc. The cache 10 is disconnected fromthe sense lines, but holds the data of, for example, row RA₁. The tagcircuit 28 holds the matching row address RA₁.

[0068] The first cycle illustrated in FIG. 4 is a miss cycle in whichnew data are loaded into the sense amplifiers, while the cache 10continues to hold the data of row RA₁.

[0069] When row address RA₀ is input, the control circuit 26 compares itwith the address RA₁ stored in the tag circuit 28 and finds that the twodo not match. Since no data are currently held in the sense amplifiers,the control circuit 26 outputs row address RA₀ to the address decoder30, which drives the corresponding word line WL0 to the active state.The data (electrical charges) in the memory cells 4 in row RA₁ arethereby transferred onto the bit lines, causing a slight potentialdivergence on each pair of complementary bit lines BLi and {overscore(BL)}i, as shown in the drawing.

[0070] Next, the control circuit 26 activates control line TG, turningon the transistors 9 in the transfer circuit 8, and activates controlline SAE, enabling the sense amplifiers 16. The pairs of bit lines BLiand {overscore (BL)}i are accordingly coupled to the sense lines Si and{overscore (S)}i and the potential differences on them are amplified.The data in one row of memory cells have now been read onto the senselines Si and {overscore (S)}i and amplified.

[0071] A series of column addresses CA₀₀, CAo₀₁, and CA₀₂ is now inputand decoded by the column decoder 32, causing it to generate three readcolumn signals RCL. Although all three RCL signals are shown forconvenience on a single line in FIG. 4, this represents three readcolumn signals RCLi with possibly different values of “i,” designatingdifferent columns. Each read column signal couples one pair of senselines Si and {overscore (S)}i to the read data lines RDB and {overscore(RDB)} and transfers the corresponding data D₀₀, D₀₁, and D₀₂ onto thesedata lines.

[0072] Control line SW is left inactive throughout this load cycle,retaining the data of row RA₁ in the cache 10. At the end of the cycle,word line WL0 and control lines TG and SAE are left active, and thesense amplifiers 16 remain enabled.

[0073] Next, the same row address RA₀ is input again, and asense-amplifier hit cycle commences. The control circuit 26 recognizesthat the input row address matches the row address of the data presentin the sense amplifiers 16, so it leaves word line WL0 and control linesTG and SAE active. Column addresses CA₀₃, CA₀₄, and CA₀₅ are input, anddata D₀₃, D₀₄, and D₀₅ from three more columns are output onto the readdata lines RDB and {overscore (RDB)}. These data can be accessed veryrapidly because they are already amplified and present on the senselines Si and {overscore (S)}i.

[0074] The cache control signal SWc remains inactive throughout thiscycle as well, and the cache 10 continues to hold the data of row RA₁.

[0075] In the next cycle, row address RA₁ is input and a cache hit cycletakes place.

[0076] Recognizing that row address RA₁ differs from the row address RA₀of the data in the sense amplifiers 16, the control circuit 26deactivates word line WL0 and control lines TG and SAE. When SAE goeslow, EQS goes high and the sense lines Si and {overscore (S)}i areequalized. This does not affect the bit lines, because the transfercircuit 8 is switched off and the bit lines are disconnected from thesense lines.

[0077] In the memory cell array 2, when WL0 has gone low, the storageelements in the memory cells in row RA₀ are disconnected from the bitlines, but they continue to store the data that were on the bit lines.Control line EQB is now driven active and the bit lines are equalized toHVcc, as shown in the drawing.

[0078] The term “precharge” will be used hereinafter to denote the twooperations of deactivating the currently-active word line and thenequalizing the bit lines to HVcc. The length of interval 46 is theprecharge time of the memory cell array 2.

[0079] After the sense lines Si and {overscore (S)}i have beenequalized, the sense amplifiers 16 are again enabled and control line SWis activated. Since REF is inactive, this activates control line SWc,permitting transfer of charge from the cache cells 12 to the sense linesSi and {overscore (S)}i. The data in the cache 10 are thus recalled ontothe sense lines Si and {overscore (S)}i and amplified. This recall ofthe cached data can be completed more quickly than the reading of datafrom the memory cell array 2, because the sense lines Si and {overscore(S)}i are shorter than the bit lines BLi and {overscore (BL)}i and haveless capacitance, and because the potential swing created on the senselines by the cache cells 12 is greater than the potential swing createdon the bit lines and sense lines by the memory cells 4. The senseamplifiers 16 can accordingly amplify data stored in the cache 10 fasterthan they can amplify data stored in the memory cell array 2.

[0080] Moreover, recall of the cached data can begin while the memorycell array 2 is still being precharged, as shown. This also speeds upthe response to a cache hit.

[0081] As soon as the cached data have been recalled onto the senselines, they are available for output in response to column addressesCA₁₀, CA₁₁, and CA₁₂. At a certain point during the output, control lineTG is reactivated and word line WL1 is driven, coupling the sense linesvia the bit lines to the memory cells 4 in row RA₁. One reason for thisis to refresh the data in row RA₁ of the memory cell array 2. Anotherreason is to update the memory cell contents in any columns in which awrite access occurs. As a result, when the cache hit cycle ends, validdata for the accessed row are not only present in the sense amplifiers16 and cache 10, but have also been copied back to the memory cell array2, maintaining data consistency between the memory cell array 2 andcache 10.

[0082] At the end of this cycle the sense amplifiers 16 are leftenabled, word line WL1 is left active, and control lines TG and SWc areleft active, in case the same row address RA₁ is input again in the nextcycle.

[0083] In the next cycle illustrated, however, the row address RA₂matches neither the address (RA₁) of the data in the sense amplifiers 16nor the address (also RA₁) of the data in the cache 10, so a replacecycle begins.

[0084] At the beginning of this cycle, control lines TG and SAE aredeactivated, disconnecting the memory cell array 2 from the sense linesSi and {overscore (S)}i and disabling the sense amplifiers 16. The senselines Si and {overscore (S)}i and connected cache cells 12 are equalizedto HVcc, and the memory cell array 2 is precharged, storing the data ofthe previous cycle in the memory cells 4 of row RA₁.

[0085] At the end of the precharge interval 48, the control circuit 26outputs row address RA₂ to the row decoder 30, which drives word lineWL2, transferring data from the memory cells in row RA₂ onto the bitlines BLi and {overscore (BL)}i. Then control signals TG and SAE areactivated to read these data onto the sense lines Si and {overscore(S)}i and amplify them. The amplified data become available for outputin response to column addresses CA₂₀, CA₂₁, and CA₂₂. Control line SW isalso activated, so the amplified data are stored in the cache 10. Thatis, the cache contents are replaced, so that instead of holding the datafor row RA₁, the cache 10 now holds the data for row RA₂. The reason formaking this replacement is so that in a refresh cycle or standby, thecache 10 will retain the most recently accessed data.

[0086] The next cycle is a refresh cycle, to refresh the data in rowRAr0. Control line TG is deactivated and the memory cell array 2 isprecharged. Control line SAE is deactivated and EQS is activated,disabling the sense amplifiers 16 and equalizing the sense lines Si and{overscore (S)}i. Then word line WLr0 and control lines TG and SAE areactivated, and the sense amplifiers amplify and refresh the data in rowRA_(r0).

[0087] When the REF signal goes high at the beginning of the refreshcycle, it deactivates control signal SWc. This signal remains inactivefor the entire duration of the refresh cycle. At the end of the refreshcycle, accordingly, although the data for row RA₂ have been lost fromthe sense amplifiers, they are retained in the cache 10. If the nextaccess is again to row RA₂, the data can be recalled quickly from thecache 10 instead of having to be read from the memory cell array 2.

[0088] Thus when the same row is accessed repeatedly, even if theaccesses are interrupted by standby intervals in which the senseamplifiers are disabled and the sense lines Si and {overscore (S)}i areequalized, or refresh cycles in which the sense amplifiers acquire thedata of a different row, after each interruption the required data canbe quickly recalled from the cache 10.

[0089] To retain data in the standby state, the control circuit 26refreshes the cache 10 by periodically activating the SAE and SW controllines, and refreshes the memory cell array 2 by periodically activatingthe word lines, SAE, and TG, in response to refresh addresses generatedby a counter (not shown). Alternatively, instead of refreshing the cache10, the control circuit 26 may abandon the cache contents after acertain time, by resetting a flag in the tag circuit 28 to indicate thatthe cache contents are no longer valid.

[0090]FIG. 5 is a block diagram showing a DRAM with a larger cache,capable of storing two rows of data. Elements identical to elements inFIG. 1 have the same reference numerals, and descriptions will beomitted.

[0091] The cache 10 in this DRAM has two rows of cache cells, so thereare two cache cells 12 ₁ and 12 ₂ per column. The tag circuit 28 in thecontrol circuit 26 accordingly has two tag memories 29 ₁ and 29 ₂, whichstore the row addresses of data held in cache cells 12 ₁ and 12 ₂,respectively, and output corresponding control signals SW1 and SW2.These are fed through respective NAND gates 34 ₁ and 34 ₂ and inverters36 ₁ and 36 ₂ to generate two cache control signals SWc1 and SWc2.Besides storing row addresses, the tag memories 29 ₁ and 29 ₂ store flaginformation indicating whether the corresponding cache rows are occupiedor empty.

[0092] The cache cells such as cell 12 ₁ coupled to control line SWc1will be referred to as the first row of cache cells, or the first cacherow; the cache cells such as cell 12 ₂ coupled to control line SWc2 asthe second row of cache cells, or the second cache row.

[0093] The cache cells in FIG. 5 are of the type shown in FIG. 2, cachecell 12 ₁ being coupled to sense line Si and cache cell 12 ₂ to senseline {overscore (S)}i. This arrangement saves space, but otherarrangements are possible. For example, both cache cells 12 ₁ and 12 ₂could be of the type shown in FIG. 3.

[0094] The operation of this DRAM will be described with reference tothe timing diagram in FIG. 6.

[0095]FIG. 6, like FIG. 4, starts from a standby state in which the dataof row RA₁ are cached. The cached data are held in the first cache row,controlled by signal SWc1. The second cache row is empty.

[0096] The sense amplifier load cycle and sense amplifier hit cycle inFIG. 6 are the same as in FIG. 4, except that control line SWc2 isactivated, so the data loaded from the memory cell array 2 into thesense amplifiers 16 are also loaded into the second row of cache cells12 ₂.

[0097] The cache hit cycle that follows is also identical to the one inFIG. 4, except that control line SWc2 is deactivated at the beginning ofthe cycle. so that while the data with row address RA₁ are beingrecalled from the first cache row, the data with row address RA₀ remainheld in the second cache row.

[0098] Accordingly, when access reverts from row RA₁ to row RA₀ in thenext cycle, another cache hit occurs. The data of row RA₀ are nowrecalled quickly from the second cache row, instead of having to be readfrom the memory cell array 2. This is done by deactivating control lineSWc1, and activating control line SWc2 again. In both cache hit cycles,the relevant word line (WL1 in the first cache hit cycle, WL0 in thesecond) is activated to refresh the data in the memory cell array 2 andstore any updates that might occur due to write access, therebymaintaining data consistency between the memory cell array 2 and cache10.

[0099] In a replace cycle, when the row address RA₂ does not match therow of data held in the sense amplifiers 16 or in either cache row, thecontrol circuit 26 selects the cache row holding the least recentlyaccessed data, and replaces the data in that row. In the present case,the data in the first cache row are replaced by activating control lineSWc1.

[0100] In a refresh cycle, the REF signal deactivates both cache controllines SWc1 and SWc2, and the existing contents of both cache rows areretained. Access to both rows of data held in the cache 10 canaccordingly resume quickly after the refresh.

[0101] This DRAM is particularly effective when access alternatesbetween two rows, because it allows the data of both rows to be cachedfor quick recall.

[0102]FIG. 7 shows a DRAM in which the memory cell array is divided intotwo banks, a left bank 2L and a right bank 2R. A single cache 10 andsense amplifier row 14 are disposed between and shared by the two banks2L and 2R. The cache 10 now has four cache cells 12 ₁, 12 ₂, 12 ₃, and12 ₄ per column; that is, there are four rows of cache cells. The twobanks 2L and 2R share the same column switching circuits 20, and havethe same column addresses. The sense lines Si and {overscore (S)}i arecoupled to banks 2L and 2R by respective transfer circuits 8L and 8R,which are controlled by respective control lines TGL and TGR.

[0103] The two banks 2L and 2R have separate row addresses, separate rowdecoders 30L and 30R, and separate bank control circuits 27L and 27R.These bank control circuits are similar to the control circuit 26 inFIGS. 1 and 5, except that the tag circuit 28 is now external to them.This enables the same tag circuit 28 to be shared by both bank controlcircuits 27L and 27R.

[0104] The tag circuit 28 has four tag memories 29 ₁, 29 ₂, 29 ₃, and 29₄, storing the row addresses of data held in the four cache rows. Thefour tag memories 29 ₁, 29 ₂, 29 ₃, and 29 ₄ generate respective controlsignals SWc1, SWc2, SWc3, and SWc4 that control the cache rows. Althoughnot explicitly shown, the tag circuit 28 also contains logic gatessimilar to the inverters and NAND gates in FIGS. 1 and 5 fordeactivating control signals SWc1, SWc2, SWc3, and SWc4 during refreshcycles, and other circuits for adjusting the timing of control signalsSWc1, SWc2, SWc3, and SWc4. The tag circuit 28 receives address inputdirectly from the address multiplexer 24.

[0105] Bidirectional signal lines XL and XR enable the bank controlcircuits 27L and 27R to learn when a cache hit occurs, and directoperations such as cache replacement. The bank control circuits 27L and27R generate the control signals TGL and TGR, as well as control signalsEQBL and EQBR to equalize the bit lines in their respective memory banks2L and 2R, and sense amplifier enable signals SAEL and SAER. A switch 49controlled by the address multiplexer 24 selects either SAEL or SAER togenerate the signals SAE and EQS that control the sense amplifier row14.

[0106] Elements in FIG. 7 not mentioned above are similar to theelements in FIGS. 1 and 5 with the same reference numerals. Omitted tosimplify the drawing is a sense-amplifier tag circuit that stores therow address of the data currently held in the sense amplifiers 16.

[0107] When a row address is input, the address multiplexer determineswhich bank 2L or 2R the address lies in, sends the address to theappropriate bank control circuit 27L or 27R, and sets switch 49 to thecorresponding position. The row address is also sent to the tag circuit28, which responds by reporting hit or miss to the bank controlcircuits. Subsequent operational details are similar to those of theDRAM in FIG. 5, so a timing diagram will be omitted.

[0108] The cache 10 in FIG. 7 can be employed in various ways. In onepreferred scheme, any of the cache cells 12 ₁, 12 ₂, 12 ₃, and 12 ₄ canhold data from either memory bank 2L or 2R. For example, all four cacherows can hold data from the same bank, or three cache rows can hold datafrom one bank while the fourth row holds data from the other bank, ortwo cache rows can be used for each bank. This full associativity of thecache 10 results in a high cache hit rate and improves the average dataaccess speed.

[0109] In another possible scheme, two of the cache rows, e.g. the twoleft rows containing cache cells 12 ₁ and 12 ₂, are reserved for storingdata from the left bank 2L. The other two cache rows are reserved forstoring data from the right bank.

[0110] The concept shown in FIG. 7 can be extended by providingadditional memory banks and sense amplifier rows, disposed in analternating arrangement. Each memory bank can then be served by twoadjacent rows of sense amplifiers, so that each sense amplifier rowneeds sense amplifiers for only one half of the columns. Each senseamplifier row has its own cache.

[0111] As mentioned above, one of the advantages of the invented cachingscheme is that when a cache hit occurs, cache access can start beforethe precharging of the memory cell array is completed. Nor is itnecessary to wait for existing data to be copied back from the senseamplifiers to the memory cells, because this copy-back is complete atthe end of each access cycle, as illustrated in FIGS. 4 and 6. However,cache access still has to wait for the equalization of the sense lines.

[0112]FIG. 8 shows a scheme for speeding up the equalization of thesense lines. Elements similar to elements in FIGS. 1 to 7 have the samereference numerals. The sense lines Si and {overscore (S)}i are showncoupled to a single memory cell array 2, but this array 2 may be dividedinto right and left banks as in FIG. 7. The cache 10 has n cache cells12 ₁, . . . 12 _(n) per column, where n may be any positive integer,from one on up. The cache cells shown are of the type in FIG. 2, butthis is not a restriction; the type in FIG. 3 or other types may be usedinstead. The tag circuit 28 has n tag memories 29 ₁, . . . 29 _(n), onefor each row of cache cells.

[0113]FIG. 8 shows a sense-amplifier equalizing circuit 50 that wasomitted to simplify FIGS. 1, 5, and 7. The sense-amplifier equalizingcircuit 50 comprises three NMOS transistors 51, 52, and 53, the gates ofwhich are all driven by the same control signal line EQSA. NMOStransistor 53 is connected across two sense-amplifier drive lines P1 andN1 its source coupled to N1 and its drain to P1. NMOS transistors 51 and52 are coupled between these two sense-amplifier drive lines P1 and N1,respectively, and a source of the intermediate potential HVcc.

[0114]FIG. 8 also shows the detailed structure of the equalizing circuit18 that equalizes the sense lines Si and {overscore (S)}i. Thissense-line equalizing circuit 18 comprises NMOS transistors 55 and 56coupled in series between the sense lines Si and {overscore (S)}i, thegates of both transistors 55 and 56 being controlled by control signalEQS. The intermediate potential HVcc is supplied through a switch 57 toa node between the two NMOS transistors 55 and 56. Switch 57 iscontrolled by control signal EQSA.

[0115]FIG. 8 furthermore shows the detailed structure of the senseamplifier 16. A sense amplifier is configured as a differentialamplifier comprising P-channel metal-oxide-semiconductor (PMOS)transistors 61 and 62 and NMOS transistors 63 and 64 cross-coupledbetween the sense lines Si and {overscore (S)}i. The sources of PMOStransistors 61 and 62 are coupled to drive line P1, which receives thepower-supply potential Vcc through a switch 65. The sources of NMOStransistors 63 and 64 are coupled to drive line N1, which receives theground potential through a switch 66. Switches 65 and 66 are controlledby the sense-amplifier enable signal SAE. The drive lines P1 and N1 arealso coupled through capacitors 67 and 68 to fixed potentials such asthe ground potential, to stabilize the sense-amplifier drivingpotentials.

[0116] The sense lines Si and {overscore (S)}i have intrinsiccapacitances, which are indicated in FIG. 8 by capacitor symbols Casiand Cbsi. These symbols do not denote separate capacitors connected tothe sense lines. Rather, they denote the so-called stray capacitance ofthe sense lines themselves.

[0117] Control signal EQSA is generated from control signal EQS by adelay circuit 70 that inputs EQS and outputs EQSA. This delay circuit ispreferably configured so that the rise of EQSA is delayed from the riseof EQS, but EQSA and EQS fall together. Delay circuits of this type arewell known: one possible configuration comprises an even number ofinverters coupled in series with an AND gate.

[0118] The sense-amplifier drive lines P1 and N1 extend in the rowdirection and are coupled to all sense amplifiers 16 in the senseamplifier row 14. Similarly, switch 57 controls the supply of the HVccpotential to all equalizing circuits 18 in the sense amplifier row 14.

[0119]FIG. 9 is a timing diagram illustrating the equalization of thesense lines in two cache hit cycles. On the address bus ADD at the topof FIG. 9, X₁ and X₂ are row addresses matching the addresses in tagcircuits 29 ₁ and 29 ₂, indicating that the data addressed by X₁ and X₂are held in the first two rows in the cache 10. Row address X₀ is a rowaddress for which data were not held in the cache 10, resulting inaccess to the memory cell array 2. Column addresses are omitted, sincethey are not relevant to the equalization process.

[0120] Access to row X₀ results in word line WLm being activated, andthe data from its coupled memory cells being read from the memory cellarray 2 onto the sense lines Si and {overscore (S)}i and amplified.Signal line SAE is active to enable the sense amplifiers 16, while EQSand EQSA are inactive. The Vcc and Vss (ground) potentials areaccordingly supplied to the sense-amplifier drive lines P1 and N1, andthe sense lines Si and {overscore (S)}i are not equalized.

[0121] When row address X₁ is input and a cache hit occurs, controlsignals TG and SAE are deactivated, placing the transfer circuit 8 inthe off state, and turning off the switches 65 and 66 in the senseamplifiers. The sense-amplifier drive lines P1 and N1 are therebydisconnected from the power supply and ground, but they remain for thetime being at their existing Vcc and Vss potentials. Word line WLm isalso deactivated and the memory cell array 2 is precharged.

[0122] Shortly after control line SAE becomes inactive, control line EQSbecomes active, turning on transistors 55 and 56 in the equalizingcircuit 18. The opposite charges stored in the stray capacitances Casiand Cbsi of the sense lines Si and {overscore (S)}i now begin todischarge toward each other through these transistors 55 and 56. Thisevent is indicated by arrow 71 in FIG. 9. For example, if sense line Siis high while {overscore (S)}i is low, then charge is transportedthrough transistors 55 and 56 from sense line Si to sense line{overscore (S)}i, causing the potential of sense line {overscore (S)}ito rise and the potential of sense line Si to fall.

[0123] In the sense amplifier 16, because Si was high and {overscore(S)}i low, transistors 61 and 64 were turned on, while transistors 62and 63 were turned off. When the potential of sense line Si falls belowVcc−V_(tp) (where V_(tp) is the PMOS threshold value), PMOS transistor62 turns on, allowing charge to flow from sense-amplifier drive line P1,which is still at Vcc, onto sense line {overscore (S)}i, therebyaccelerating the equalization of sense line {overscore (S)}i. This isindicated by arrow 72 in FIG. 9. Likewise, when the potential of senseline {overscore (S)}i rises above the NMOS transistor threshold valueV_(tn), transistor 63 turns on, and charge can flow from sense line Sito the ground-level sense-amplifier drive line N1, as indicated by arrow73. Thus the charges remaining on sense-amplifier drive lines P1 and N1are used to speed up the equalization of sense lines Si and S{overscore(i)}.

[0124] After a delay due to the delay circuit 70, control line EQSAbecomes active, turning on transistors 51, 52, and 53 in thesense-amplifier equalizing circuit 50, and supplying HVcc to thesense-amplifier drive lines P1 and N1. EQSA also turns on switch 57 andsupplies the intermediate potential HVcc to the sense-line equalizingcircuits 18. The sense-amplifier drive lines P1 and N1 and sense linesSi and {overscore (S)}i are thereby all equalized to HVcc.

[0125] As explained above, delaying the activation of control signalEQSA accelerates the equalization of the sense lines Si and {overscore(S)}i by providing additional charge and discharge paths 72 and 73through the sense amplifier 16. These paths would not exist if thesense-amplifier drive lines P1 and N1 were equalized immediately toHVcc. In the case described above, transistors 62 and 63 would not turnon; the gate potential of NMOS transistor 63, for example, would belower than its HVcc source potential.

[0126] After equalization is completed, signals EQS and EQSA aredeactivated simultaneously, control signal SWc1 is activated, and thedata in the first cache row are read onto the sense lines Si and{overscore (S)}i. Control line SAE is activated, the sense-amplifierdrive lines P1 and N1 are powered, and the cached data are amplified.Column addresses (not indicated in FIG. 9) can then be input to accessthe data.

[0127] The next access cycle is a cache hit by row address X₂. Controlsignal SWc1 is deactivated, and the pair of sense lines Si and{overscore (S)}i are equalized in the same rapid manner as before. Thisis followed by activation of control signal SWc2 and access to the datain the second cache row.

[0128] The quick equalization of sense lines Si and {overscore (S)}i dueto the delay of EQSA from EQS is beneficial in cache miss cycles as wellas cache hit cycles, but it is particularly valuable in permitting rapidaccess to the cache 10.

[0129]FIG. 10 shows a scheme for further speeding up access to the cache10, and reducing current dissipation. Elements which are the same aselements in FIG. 8 have the same reference numerals.

[0130] In FIG. 10 the sense-amplifier equalizing circuit 50 and switch57 are activated by separate control signals EQSA and EQSL, which haverespective delay circuits 70 and 74. The inputs EQS2 and EQS3 to thesedelay circuits 70 and 74 are generated by a hit/miss detector 75, thefunction of which is to prevent activation of the sense-amplifierequalizing circuit 50 in a cache-hit cycle.

[0131]FIG. 11 shows an example of the internal structure of the hit/missdetector 75. This hit/miss detector 75 comprises a hit detector 76 thatoutputs an internal signal EQS1, a miss detector 77 that outputs controlsignal EQS2, and a logic circuit, more specifically an OR gate 78, thattakes the logical OR of EQS1 and EQS2 to generate control signal EQS3.

[0132] The hit detector 76 receives, for example, a hit/miss flag signalfrom the tag circuit 28, and activates signal EQS1 when a cache hitoccurs. The miss detector 77 also receives the hit/miss flag signal,together with a REF signal indicating a refresh cycle, and a STBY signalindicating standby. Control signal EQS2 is activated when a cache missoccurs, or a refresh cycle occurs, or the standby state is entered.

[0133] The hit detector 76 and miss detector 77 also receive signalsindicating occurrence of a sense-amplifier hit, in which case neitherEQS1 nor EQS2 is activated, because the data are already present in thesense amplifiers 16.

[0134]FIG. 12 is a timing diagram illustrating equalization of the senselines in two cache hit cycles by the circuits shown in FIGS. 10 and 11.Row addresses X₀, X₁, and X₂ have the same meaning as in FIG. 9.

[0135] Equalization of the sense lines Si and {overscore (S)}i proceedsas in FIG. 9, speeded by the transfer of charge between the sense linesSi and {overscore (S)}i and the sense-amplifier drive lines P1 and N1.After a delay due to delay circuit 74, control line EQSL is activatedand the sense lines Si and {overscore (S)}i are brought to HVcc. In ahit cycle, however, control line EQSA remains inactive, so HVcc is notsupplied to the sense-amplifier drive lines P1 and N1.

[0136] Assuming again that sense line Si was high and {overscore (S)}ilow, when the potential on sense-amplifier drive line P1 falls toHVcc+V_(tp), the potential on sense line Si, which is at least HVcc, canno longer turn on PMOS transistor 62, so no more charge flows fromsense-amplifier drive line P1 to sense line {overscore (S)}i. Similarly,when the potential on sense-amplifier drive line N1 reaches HVcc−V_(tn),NMOS transistor 63 turns off, and the flow of charge from sense line Sito sense-amplifier drive line N1 ceases. Sense-amplifier drive line P1therefore remains at HVcc +V_(tp), while sense-amplifier drive line N1remains at HVcc−V_(tn).

[0137] When equalization of the sense lines Si and {overscore (S)}i hasended, sense-amplifier drive lines P1 and N1 remain unequalized atHVcc+V_(tp) and HVcc−V_(tn), and control line SWc1 is activated by thetag circuit 28. Since the sense lines are short and their intrinsiccapacitances Casi and Cbsi are comparatively small, the charge in cachecell 12 ₁ produces a fairly large potential swing on sense line Si.Accordingly, when control line SAE is activated to supply power to thesense amplifier 16, even though the sense amplifier drive lines P1 andN1 were not fully equalized, the potential difference between senselines Si and {overscore (S)}i is large enough to be amplified correctly.

[0138] In the following cache hit cycle the same process is repeated toaccess the data in cache cell 12 ₂. The sense-amplifier drive lines P1and N1 are again left unequalized.

[0139] When control line SAE is activated to amplify the cached data(arrow 79), control line TG must be inactive so that the senseamplifiers 16 do not have to contend with the large stray capacitance ofthe bit lines BLi and {overscore (BL)}i. After amplification iscompleted, although not shown in FIG. 12, control line TG can beactivated to copy data back from the sense lines Si and {overscore (S)}ito the memory cells 4.

[0140] Omitting the equalization of the sense-amplifier drive lines P1and N1 makes it possible to advance very quickly to the access of cacheddata. In addition, not equalizing the sense-amplifier drive lines P1 andN1 reduces current dissipation in a cache hit.

[0141]FIG. 13 illustrates the equalization operations performed by thecircuits in FIGS. 10 and 11 in a cache miss cycle.

[0142] After a cache hit on, for example, the third cache row caused byrow address X₃, the next row address X₄ does not match the address heldin any tag memory, so the memory cells 4 must be accessed. Control lineSWc3 is deactivated by the tag circuit 28, control line SAE isdeactivated, switches 65 and 66 in sense amplifier 16 are placed in theoff state, and sense-amplifier drive lines P1 and N1 are disconnectedfrom the power supply and ground. The hit/miss detector 75 activatescontrol lines EQS2 and EQS3, and after a delay inserted by the delaycircuit 74, control line EQSL is activated, equalizing the sense linesSi and {overscore (S)}i. Delay circuit 70 keeps control line EQSAinactive during this time so as to speed up the equalization by usingthe charge remaining on the sense-amplifier drive lines P1 and N1, asalready explained.

[0143] After the sense lines Si and {overscore (S)}i have beenequalized, the delay circuit 70 activates control line EQSA, equalizingthe sense-amplifier drive lines P1 and N1 to HVcc. Next, control linesEQS2, EQS3, EQSA, and EQSL are deactivated, control line TG is activatedto couple the sense lines to the bit lines, the word line WL4corresponding to row address X₄ is activated, control line SAE isactivated to enable the sense amplifiers 16, and data are transferredfrom the memory cells 4 coupled to word line WL4 onto the bit lines BLiand {overscore (BL)}i and sense lines Si and {overscore (S)}i. Due tothe large capacitance of the bit lines BLi and {overscore (BL)}i, theresulting potential swing is small, but the potential difference issensed and amplified correctly by the sense amplifiers 16, because theirdrive lines P1 and N1 start from the equalized potential HVcc.

[0144] The next cycle is also a cache miss, the input row address X₅ notmatching the address in any tag circuit. Once again, this is detected bythe hit/miss detector 75, and the sense-amplifier drive lines P1 and N1as well as the sense lines Si and {overscore (S)}i are equalized to theintermediate potential HVcc.

[0145] The hit/miss detector 75 activates the sense-amplifier equalizingcircuit 50 to equalize the sense-amplifier drive lines P1 and N1 notonly in cache miss cycles, but also in refresh cycles, because inrefresh cycles as well, the sense amplifiers 16 must amplify smallpotential differences on the bit lines. Furthermore, the sense-amplifierdrive lines P1 and N1 are equalized in the standby state, to prevent theflow of unwanted leakage current.

[0146] In the embodiments shown so far, the cache has been coupleddirectly to the sense lines. Although the cache provides major benefitsby enabling quick recall of cached data. and retaining cached dataduring refresh cycles, this arrangement does not permit the cached datato be accessed during refresh cycles. Thus if the memory device has anauto-refresh function and generates its own refresh cycles, each timeone of these refresh cycles occurs, external access must be delayeduntil the refresh cycle ends.

[0147]FIG. 14 is a circuit drawing of part of a DRAM in which cachecells are disposed in the column switching circuits. Elements identicalto elements in FIGS. 1 to 10 have the same reference numerals. Althoughonly a single memory cell array 2 is shown, it may be divided into twobanks as in FIG. 7. The sense amplifier row 14 preferably has equalizingcircuits structured as in FIG. 8 or 10, but for simplicity only controllines SAE and EQS are shown.

[0148] The novel column switching circuit 200 _(i), like theconventional column switching circuit 20 in FIGS. 1 to 7, interfaces thesense lines Si and {overscore (S)}i to the read data lines RDB and{overscore (RDB)} and write data lines WDB and {overscore (WDB)}. Unlikethe conventional circuit, the column switching circuit 200 _(i) has ncache cells 12 _(i1), . . . , 12 _(in), where n may be any positiveinteger. The subscript i is being used to identify elements belonging tothe i-th column, which will be useful in discussing write access.

[0149] The cache cells 12 _(ij) are coupled to a pair of complementarycolumn data lines CDi and {overscore (CD)}i. Data transfer between thecache cells 12 _(ij) and column data lines CDi and CD{overscore (i)} iscontrolled by cache control signals SWcj (j=1, 2, . . . , n). As in thepreceding embodiments, these cache control signals are output from a tagcircuit 28 with tag memories 29 _(j) (j=1, 2, . . . , n). The cachecells 12 _(1j), 12 _(2j), . . . controlled by the same control line SWcjwill be referred to as the j-th cache row 210 _(j). FIG. 14 explicitlyindicates the first cache row 210 ₁. All of the cache cells 12 _(ij)will continue to be referred to collectively as the cache, even thoughthe cache cells 12 _(ij) are disposed in different column switchingcircuits 200 _(i).

[0150] The cache cells 12 _(ij) have, for example, the structure shownin FIG. 2 or 3, except that they are coupled to the column data linesinstead of the sense lines.

[0151] The read column line RCLi drives the gates of two NMOStransistors 219 and 220 which are coupled to read data lines {overscore(RDB)} and RDB, respectively. Two more NMOS transistors 221 and 222,with gates controlled by the column data lines CDi and {overscore(CD)}i, are coupled in series between transistors 219 and 220. Thesources of NMOS transistors 221 and 22 are supplied with a fixedpotential such as the ground potential (Vss). Transistors 221 and 222form a simple amplifier that enables a small potential swing on thecolumn data lines CDi and {overscore (CD)}i to produce a largerpotential swing on the read data lines RDB and {overscore (RDB)}.(Similar amplifiers may be employed in the column switching circuits 20of FIGS. 1 to 7.)

[0152] Sense lines Si and {overscore (S)}i are coupled to thecorresponding column data lines CDi and {overscore (CD)}i throughrespective NMOS transistors 223 and 224, the gates of which are coupledto a control line SWa. The column data lines CDi and {overscore (CD)}iare coupled to the write data lines WDB and {overscore (WDB)} throughrespective NMOS transistors 225 and 226, the gates of which are drivenby the write column line WCLi. An equalizing circuit 227, similar to thesense line equalizing circuit 18 for example, is provided to equalizethe column data lines CDi and {overscore (CD)}i. The control line of thecolumn-data-line equalizing circuit 227 is not explicitly shown, but itis different from the EQS control line of the sense-line equalizingcircuit 18, permitting the sense lines Si and {overscore (S)}i to beequalized while the column data lines CDi and {overscore (CD)}i remainunequalized, or vice versa.

[0153] First, the operation of control lines SWa, WCLi, and RCLi will bebriefly described.

[0154] When control line SWa is activated, NMOS transistors 223 and 224turn on, coupling the sense lines Si and {overscore (S)}i to the columndata lines CDi and {overscore (CD)}i, so that the same data appear onboth Si/{overscore (S)}i and CDi/{overscore (CD)}i. This occurssimultaneously in all columns. When SWa is inactive, the sense lines Siand {overscore (S)}i are disconnected from the column data lines CDi and{overscore (CD)}i.

[0155] When control line WCLi is activated, NMOS transistors 225 and 226turn on, and data present on the write data lines WDB and {overscore(WDB)}0 are transferred to the column data lines CDi and {overscore(CD)}i.

[0156] When control line RCLi is activated, transistors 219 and 220 turnon. Both read data lines RDB and {overscore (RDB)} are initiallyprecharged to a certain potential such as the power-supply potentialVcc. If data are present on the column data lines CDi and {overscore(CD)}i, so that one of these lines is high while the other is low, thenone of the NMOS transistor transistors 221 and 222 will be turned onwhile the other is turned off. If column data line CDi is high, forexample, then transistor 221 will turn on, pulling read data line{overscore (RDB)} down to the ground level. Transistor 222 will remainoff, so read data line RDB is not coupled to ground and remains high. Inthis way the data on the column data lines CDi and {overscore (CD)}i aretransferred to the read data lines RDB and {overscore (RDB)}.

[0157] Although the input-output circuits coupled to the data bus linesare not shown, these circuits should be configured so that data can betransferred from the write data lines WDB and {overscore (WDB)} to thecolumn data lines CDi and {overscore (CD)}i and then to the read datalines RDB and {overscore (RDB)}, or from the cache cells 12 _(ij) to thecolumn data lines CDi and {overscore (CD)}i and then to the read datalines RDB and {overscore (RDB)}, without amplification by the senseamplifiers 16.

[0158]FIGS. 15 and 16 illustrate the operation of the DRAM in FIG. 14 ina cache load cycle, cache hit cycle, cache replace cycle, and combinedcache hit and refresh cycle. Both read and write access are shown. Onthe address bus ADD, addresses X₀, X₁, X₂, . . . are row addresses thatselect corresponding word lines WL0, WL1, WL2, . . . , while Y_(i),Y′_(i), Y″_(i), . . . are column addresses.

[0159] A feature of the operation of this DRAM is that, as in thepreceding embodiments, the cache contents are kept consistent with thememory cell contents; in every cycle, any newly input write data arecopied back to the memory cell array 2. More precisely, all data presenton the sense lines at the end of a cycle have also been copied back tothe memory cell array 2 by the end of that cycle.

[0160] (1) Cache Load Cycle

[0161] A cache load cycle occurs when an input row address does notmatch the address of any cached data, but there exists an empty cacherow (a cache row that does not hold valid data). The data in theaddressed row are then read from the memory cell array onto the senselines, and also loaded into the empty cache row, as follows.

[0162] Referring to FIG. 15, if row address X₀ does not match the rowaddress held in any tag memory 29 _(j), and cache row 210 ₁ is empty,then the tag circuit 28 drives control line SWc1 to the active state.The word line WL0 corresponding to row address X₀ is also activated.Transfer circuit 8 is turned on by control line TG, so the data DA1 inrow X₀ are read out of their memory cells via the bit lines BLi and{overscore (BL)}i and amplified, thus appearing on the sense lines Siand {overscore (S)}i. Control line SWa is active, so the sense lines arecoupled to the column data lines CDi and {overscore (CD)}i, on whichdata DA1 also appear. Since control line SWc1 is active, the data DA1are loaded into the first cache row 210 ₁.

[0163] Next, an external read/write control signal (not shown) is placedin the read state, and a column address Y_(i) is input. This activatesthe corresponding read column line RCLi, transferring data DA1 onto thepair of read data lines RDB and {overscore (RDB)} as explained above.Since the NMOS transistors 221 and 222 that drive the read data linesRDB and {overscore (RDB)} act as amplifiers, data DA1 can be read ontothe read data lines RDB and {overscore (RDB)} even before amplificationby the sense amplifier 16 is completed.

[0164] The read/write signal is now placed in the write state to writeto the same column address Y_(i). This causes the write control lineWCLi in the i-th column to go high, transferring data DA2 from the pairof write data lines WDB and {overscore (WDB)} to the pair of column datalines CDi and {overscore (CD)}i, thence to cache cell 12 _(i1) in cacherow 210 ₁ and the pair of sense lines Si and {overscore (S)}i. Controlline TG remains active, so data DA2 are transferred from the sense linesSi and {overscore (S)}i to the bit lines BLi and {overscore (BL)}i andcopied back into the corresponding memory cell. At most one pair of bitlines, namely BLi and {overscore (BL)}i in the i-th column, has to becharged or discharged in this copy-back operation, so it is completedquickly. As soon as BLi and {overscore (BL)}i are fully charged anddischarged, the next cycle can begin.

[0165] Control lines TG, SWa, and SWc1 and word line WL0 are left activeat the end of this cycle, so that if row address X₀ is input again,access can continue immediately using the data remaining in the senseamplifiers, sense lines Si and {overscore (S)}i, and column data linesCDi and {overscore (CD)}i.

[0166] Although the same column address Y_(i) was accessed for both readand write above, the read and write column addresses can of course bedifferent. Nor is the cycle limited to one read access and one writeaccess; multiple read accesses and multiple write accesses to differentcolumns in the same row are possible. There is no restriction on theorder of accesses; read may precede write, or vice versa.

[0167] (2) Cache Hit Cycle

[0168] A cache hit cycle occurs when a new row address is input and itmatches one of the row addresses held in the tag circuit. The senselines are then disconnected from the bit lines, and the data for theaddressed row are recalled from the cache. At the end of the cycle, thebit lines are coupled to the sense lines again to write any updated databack to the memory cells.

[0169] Assume, for example, that row address X₁ matches the address heldin tag memory 29 ₂, indicating that the data of this row are currentlystored in cache row 210 ₂. Control line TG is deactivated to disconnectthe sense lines Si and {overscore (S)}i from the bit lines BLi and{overscore (BL)}i2L, and the tag circuit 28 deactivates cache controlline SWc1, disconnecting cache row 210 ₁ from the column data lines CDiand {overscore (CD)}i. The data for row address X₀ are now held in thefirst cache row 210 ₁, and are still present on the bit lines BLi and{overscore (BL)}i and their connected memory cells.

[0170] Next the sense lines Si and {overscore (S)}i and column datalines CDi and {overscore (CD)}i are equalized, then cache control lineSWc2 is activated by the tag circuit 28, transferring the data fromcache row 210 ₂ onto the column data lines CDi and {overscore (CD)}i.Control line SWa remains active, so these data are also transferred tothe sense lines Si and {overscore (S)}i and amplified by the senseamplifiers 16.

[0171] As soon as the data for row address X₁ have been recalled in thisway from the cache, read and write access can begin. Column addressY_(i) is input, and data DA3 are read onto the read data lines RDB and{overscore (RDB)}; then data DA4 are written from the write data linesWDB and {overscore (WDB)} onto the column data lines CDi and {overscore(CD)}i and sense lines Si and {overscore (S)}i in the i-th column.

[0172] While the data are being recalled from the cache, word line WL0is deactivated and the bit lines are precharged. The data for rowaddress X₀, including the updated data DA2 in the i-th column, thusremain held in both the memory cells 4 of row X₀ in the memory cellarray 2, and the cache cells 12 _(i1) of the first cache row 210 ₁.Next, control line TG is activated and word line WL1 is activated, tocopy the data of row address X₁ from the sense lines Si and {overscore(S)}i back to the memory cells 4 on word line WL1. This copy-backincludes the newly written data DA4.

[0173] Access in a cache hit cycle takes place quickly because the dataare recalled from the cache via the column data lines CDi and {overscore(CD)}i, which have a relatively small capacitance to be charged ordischarged, instead of via the bit lines BLi and {overscore (BL)}i,which have a larger capacitance and resistance. Time is also saved byprecharging the memory cell array 2 while the cached data are beingrecalled and read.

[0174] (3) Cache Replace Cycle

[0175] A cache replace cycle occurs when the input row address does notmatch the row address held in any tag memory, and there is no emptycache row. One cache row is selected for replacement. The addressed rowof data is read from the memory cell array, accessed, and written intothe selected cache row. No copy-back is necessary at the start of acache replace cycle, because the cache contents and memory-cell contentsare consistent at the end of the preceding cycle.

[0176] The cache row to be replaced can be selected according to variousalgorithms, such as the well-known least-recently-used (RLU) rule. Thepresent invention is not restricted to any particular replacementalgorithm. Here it will be assumed that cache row 210 ₁ is replaced.

[0177] In FIG. 15, input row address X₂ does not match any current tagaddress, and no empty cache row is available. The first part of thiscache replace cycle resembles a cache hit cycle. Control line SWaremains active, but control lines TG and SWc2 are deactivated, leavingthe data for the row address X₁ in the previous cycle present on the bitlines BLi and {overscore (BL)}i and in cache row 210 ₂. Next, the senselines Si and {overscore (S)}i and column data lines CDi and {overscore(CD)}i are equalized.

[0178] Control line SWc1 is now activated, coupling the cache row 210 ₁to be replaced to the column data lines CDi and {overscore (CD)}i.Equalization of the sense lines Si and {overscore (S)}i is continued,and the column data lines CDi and {overscore (CD)}i are also equalized,so the existing data in cache row 210 ₁ are lost. In the meantime thememory cell array 2 is precharged, leaving the data for row address X₁stored in the memory cells 4 of that row.

[0179] When this precharge is completed, control line TG is activated,the word line WL2 designated by the new row address X₂ is activated, thesense amplifiers 16 are enabled, and equalization of the sense lines Siand {overscore (S)}i and column data lines CDi and {overscore (CD)}i isdiscontinued. The data for row X₂ are thereby read onto the bit linesBLi and {overscore (BL)}i, transferred to the sense lines Si and{overscore (S)}i, amplified by the sense amplifiers 16, transferred tothe column data lines CDi and {overscore (CD)}i, and loaded into cacherow 210 ₁.

[0180] Read or write access now proceeds as in a cache hit cycle or loadcycle. In the drawing, data DA5 are read from the i-th column onto thedata bus.

[0181] (4) Refresh During Cache Hit Cycle

[0182] During a cache hit cycle on one row address, it is possible torefresh a different row in the memory cell array. After the cached datahave been recalled onto the column data lines and amplified, the columndata lines are disconnected from the sense lines. While read and writeaccess to the column data lines continues, the sense amplifiers can beused to refresh an arbitrary row in the memory cell array. At the end ofthe cycle, the data on the column data lines are copied back to theaddressed row in the memory cell array.

[0183] Referring to FIG. 16, input row address X₁ matches the addressheld in tag circuit 29 ₂, so a cache hit cycle is initiated. Just as inthe cache hit cycle in FIG. 15, control line TG is deactivated and thememory cell array 2 is precharged. Control line SWc1 is also deactivatedby the tag circuit 28. As a result, the data (e.g. DA5) left on thecolumn data lines CDi and {overscore (CD)}i at the end of the precedingcycle are saved in the memory cells 4 coupled to word line WL2 and thecache cells 12 _(i1) in cache row 1. Concurrently with these operations,the sense lines Si and {overscore (S)}i and column data lines CDi and{overscore (CD)}i are equalized: then the control line SWc2 of the cacherow 210 ₂ that was hit by the new row address X₁ is activated by the tagcircuit 28, the sense amplifiers 16 are enabled, and data are recalledfrom cache row 210 ₂ onto the column data lines CDi and {overscore(CD)}i and sense lines Si and {overscore (S)}i.

[0184] In preparation for refreshing a row in the memory cell array,control line SWa is now deactivated, disconnecting the sense lines Siand {overscore (S)}i from the column data lines CDi and {overscore(CD)}i. Read and write accesses continue to be carried out in the usualway, by input of column addresses, except that in write access, thewritten data are not amplified by the sense amplifiers. Thus when dataDA6 are written in the i-th column, for example, the resulting swing onthe column data lines CDi and {overscore (CD)}i is less than in FIG. 15.This does not prevent subsequent read access from taking place, becausethe reduced swing is still adequate to drive the NMOS transistors 221and 222 and place the new data on the read data lines RDB and {overscore(RDB)}. After the reading of data DA4 and writing of data DA6, furthercolumn addresses are input and read and write access continues in thesame or other columns.

[0185] While this access to the column data lines CDi and {overscore(CD)}i is taking place, the sense amplifiers 16 are disabled and thesense lines Si and {overscore (S)}i are equalized. Next, after the senselines Si and {overscore (S)}i and bit lines BLi and {overscore (BL)}ihave both been equalized, control line TG is reactivated, turning on thetransfer circuit 8. Simultaneously, a word line to be refreshed isselected by an internal refresh counter and activated. This word line isunrelated to the current input row address X₁; in the drawing, word lineWL3 is refreshed.

[0186] After word line WL3 has been activated, the sense amplifiers 16are enabled again, and the data in the memory cells 4 coupled to wordline WL3 are amplified on the bit lines BLi and {overscore (BL)}i andsense lines Si and {overscore (S)}i. When amplification is complete,control line TG is deactivated to disconnect the bit lines BLi and{overscore (BL)}i from the sense lines Si and {overscore (S)}i, and thememory cell array 2 is precharged, leaving refreshed data in the memorycells 4 coupled to word line WL3.

[0187] After control line TG has been deactivated and the transfercircuit 8 has been turned off, the sense amplifiers 16 are disabled andthe sense lines Si and {overscore (S)}i are equalized. Then control lineSWa is activated again, coupling the column data lines CDi and{overscore (CD)}i to the sense lines Si and {overscore (S)}i, and thesense amplifiers are enabled. Data such as DA6 on the column data linesCDi and {overscore (CD)}i are now amplified to obtain a full potentialswing.

[0188] When the memory cell array 2 has been precharged, control line TGis activated again, transferring the amplified data such as DA6 to thebit lines BLi and {overscore (BL)}i. Then word line WL1 is activated tocopy the amplified data back to the memory cells in row X₁ in the memorycell array.

[0189] If a refresh cycle cannot be scheduled to coincide with a cachehit cycle, then a conventional refresh operation is carried out, andexternal access is delayed.

[0190] The advantages of placing the cache cells in the column switchingcircuits can be summarized as follows.

[0191] First, refresh cycles can be executed within cache hit cycles.Refresh can then be carried out without impairing response speed, andthe average data rate can be improved.

[0192] Second, precharging of the memory cell array 2 and the recall ofdata onto the column data lines CDi and {overscore (CD)}i can be carriedout concurrently, by disconnecting the bit lines from the sense lines.The enables a shortening of the minimum cycle time (the time from inputof one row address until input of the next row address can be accepted).

[0193]FIG. 17 is a circuit drawing of part of another novel DRAM.Elements which are the same as elements in FIG. 14 have the samereference numerals.

[0194] The only difference between FIGS. 14 and 17 is that in the DRAMin FIG. 17, a write buffer 300 is provided between the sense lines Siand {overscore (S)}i. The write buffer 300 comprises a switching element301 such as an NMOS transistor coupled to sense line Si, a switchingelement 302 such as another NMOS transistor coupled to sense line{overscore (S)}i, and a storage element 303 such as a capacitor coupledbetween these switching elements 301 and 302. Switching elements 301 and302 are controlled by a common control line SWb, which extends in therow direction and controls the write buffers 300 in all columnssimultaneously.

[0195] The write buffers require only a small amount of additionalcircuit space, and enable cache access and copy-back can be executedconcurrently. Copy-back operations can furthermore be advantageouslydeferred until made necessary by cache replacement.

[0196]FIGS. 18 and 19 illustrate the operation of this DRAM in a cacheload cycle, cache hit cycle, cache replace cycle, and combined refreshand cache hit cycle. A feature of these operations is that the cache andmemory cell array are allowed to become inconsistent.

[0197] (1) Cache Load Cycle

[0198] The main difference between the cache load cycle in FIG. 18 andthe one in FIG. 15 is that in FIG. 18, control line TG is activated onlylong enough to transfer the data of row X₀ from the bit lines BLi and{overscore (BL)}i to the sense lines Si and {overscore (S)}i. As soon asthis transfer is completed, control line TG is deactivated again,disconnecting the bit lines BLi and {overscore (BL)}i from the senselines Si and {overscore (S)}i, and the memory cell array 2 isprecharged.

[0199] At the point when control line TG is deactivated and the transfercircuit 8 is turned off, amplification of the signals on the bit linesBLi and {overscore (BL)}i and sense lines Si and {overscore (S)}i hasbarely begun, so the potential swing on the bit lines BLi and {overscore(BL)}i is still small. Equalization of the bit lines BLi and {overscore(BL)}i is accordingly completed in a very short time, with relativelylittle current dissipation. The current drawn by the sense amplifiers 16is also greatly reduced, since they do not have to charge and dischargethe bit lines BLi and {overscore (BL)}i.

[0200] Control signal SWa is active throughout this cycle, so the datatransferred to the sense lines Si and {overscore (S)}i are alsotransferred to the column data lines CDi and {overscore (CD)}i. At anappropriate point, control line SWc1 is activated to store these data inthe empty cache row 210 ₁. In addition, column addresses Y_(i) are inputand read and write accesses take place as in FIG. 15. As in FIG. 15,read or write access can begin even before the data have been fullyamplified, and write access can be further speeded up because it is notnecessary to charge or discharge the bit lines BLi and {overscore(BL)}i.

[0201] In FIG. 18, precharging of the memory cell array 2 is completedeven before the end of the first read access (that is, before the readcolumn line RCLi goes low). The memory is accordingly ready to begin anew cycle at this point; a new row address could now be input, so theminimum cycle time is very short.

[0202] At the end of the cache load cycle in FIG. 18, the data for rowaddress X₀, including the newly written data DA2, are present on thesense lines Si and {overscore (S)}i and column data lines CDi and{overscore (CD)}i, and in cache row 210 ₁. but are not held in thememory cell array 2.

[0203] (2) Cache Hit Cycle

[0204] The cache hit cycle in FIG. 18 is identical to the one in FIG.15, except that control line TG is inactive, the transfer circuit 8 isin the off state throughout the cycle, and there is no activity in thememory cell array 2. Read and write access are confined completely tothe column data lines CDi and {overscore (CD)}i and sense lines Si and{overscore (S)}i. Write access can be speeded up, current dissipationreduced, and the minimum cycle time shortened, because there is no needto charge or discharge any pair of bit lines BLi and {overscore (BL)}ior activate or deactivate any word lines.

[0205] At the end of the cache hit cycle in FIG. 18, data for rowaddresses X₀ and X₁ are held in cache rows 210 ₁ and 210 ₂, and thecorresponding rows in the memory cell array 2 are both invalid.

[0206] (3) Cache Replace Cycle

[0207] The cache replace cycle in FIG. 18 differs from the one in FIG.15. In FIG. 18, a cache row is selected for replacement and its data aresaved into the write buffers 300. Then the addressed row of data is readout of the memory cell array 2 onto the column data lines CDi and{overscore (CD)}i and accessed there. While access to the data on thecolumn data lines is in progress, the replaced data are copied back fromthe write buffers to the memory cell array.

[0208] At the beginning of the cycle, it is recognized that the inputrow address X₂ does not correspond to the row address in any tag memory,and that no cache row is empty, so cache row 210 ₁, for example, isselected for replacement. Control line SWc2 is deactivated, the senseamplifiers are disabled, and the column data lines CDi and {overscore(CD)}i and sense lines Si and {overscore (S)}i are equalized. Controlline SWb is activated, so that the write buffers 300 are also equalized.

[0209] Next, control line SWc1 is activated. The data (e.g. DA2) thatwill be replaced are read from cache row 210 ₁ onto the column datalines CDi and {overscore (CD)}i and sense lines Si and {overscore (S)}i,amplified by the sense amplifiers, and transferred into the writebuffers 300. After a short time, control line SWb is switched off again,leaving the data stored in the write buffers. The sense lines Si and{overscore (S)}i and column data lines CDi and {overscore (CD)}i are nowequalized once again.

[0210] While the data of row address X₀ are being transferred from cacherow 210 ₁ into the write buffers 300 in this way, the newly addressedword line WL2 is activated in the memory cell array 2, and the datastored in the memory cells 4 coupled to this word line (the data withrow address X₂) are transferred onto the bit lines BLi and {overscore(BL)}i. When the sense lines Si and {overscore (S)}i have beenequalized, control line TG is activated and the transfer circuit 8 isturned on briefly, transferring the data (e.g. DA5) for row address X₂from the bit lines BLi and BLi to the sense lines Si and {overscore(S)}i. Then control line TG is deactivated again and the memory cellarray 2 is precharged. Since the potential swing on the bit lines BLiand {overscore (BL)}i was small, the precharge time is short.

[0211] After the deactivation of control line TG, the sense amplifiers16 continue to amplify the data (DAS) on the sense lines Si and{overscore (S)}i and column data lines CDi and {overscore (CD)}i. Whenamplification is completed, control line SWa is deactivated,disconnecting the column data lines CDi and {overscore (CD)}i from thesense lines Si and {overscore (S)}i.

[0212] Read and write access can now take place using the column datalines CDi and {overscore (CD)}i alone. In the drawing, column addressY_(i) is input, data DA5 are read from the column data lines CDi and{overscore (CD)}i in the i-th column onto the read data lines RDB and{overscore (RDB)}, then data DA6 are written from the write data linesWDB and WDB onto the same pair of column data lines CDi and {overscore(CD)}i. Next other column addresses Y_(i)′ and Y″ are input and readaccess, for example, is carried out in other columns.

[0213] While this access is taking place, the sense lines Si and{overscore (S)}i are equalized again; then control line SWb is activatedand the data DA2 that were stored in the write buffers 300 aretransferred onto the sense lines Si and {overscore (S)}i and amplified.At the same time, word line WL0 is activated in the memory cell array 2.When amplification is complete, control line TG is activated, thetransfer circuit 8 is turned on, and data (e.g. DA2) are transferredfrom the sense lines Si and {overscore (S)}i via the bit lines BLi and{overscore (BL)}i to the memory cells 4 at row address X₀. When thiscopy-back is completed, control line TG is deactivated again and thememory cell array 2 is precharged.

[0214] After the control line TG is deactivated and transfer circuit 8is turned off, the sense lines Si and {overscore (S)}i are equalizedagain, then control line SWa is activated to reconnect the sense linesSi and {overscore (S)}i to the column data lines CDi and {overscore(CD)}i. The sense amplifiers 16 now amplify the data on the column datalines CDi and {overscore (CD)}i, including the newly written data DA6 inthe i-th column.

[0215] At the end of the cache replace cycle in FIG. 18, data for rowaddresses X₁ and X₂ are held in cache rows 210 ₂ and 210 ₁,respectively, while data for row address X₀ are held in the memory cellarray 2. The data for row address X₂ also remain amplified and availableon the sense lines Si and {overscore (S)}i and column data lines CDi and{overscore (CD)}i, ready for immediate access if the same row address X₂is input again.

[0216] Compared with FIG. 15, the cache replace cycle in FIG. 18 enablesa quicker transfer of the required data from the memory cell array tothe sense lines, because the newly addressed word line (WL2) can beactivated at the beginning of the cycle, without waiting for the memorycell array to be precharged.

[0217] (4) Refresh Cycle During a Cache Hit Cycle

[0218] Since there is no interchange of data between the cache andmemory cell array in a cache hit cycle, refreshing the memory cell arrayduring a cache hit cycle is a simple matter. After the required datahave been recalled, the sense lines are disconnected from the columndata lines and coupled to the bit lines, and the sense amplifiers areused to refresh an arbitrary row of memory cells.

[0219] Referring to FIG. 19, this cycle is shown as a type-1 refreshcycle. When row address X₁ is input, a hit is recognized on cache row201 ₂, so control line SWc1 is deactivated (storing data DA6 in cacherow 210 ₁), and the sense lines Si and {overscore (S)}i and column datalines CDi and {overscore (CD)}i are equalized. Then control line SWc2 isactivated, recalling the data for row address X₁ (e.g. DA4) onto thecolumn data lines CDi and {overscore (CD)}i. Control line SWa, however,is deactivated, so the recalled data are not amplified. The unamplifiedsignals are still adequate for read access, so when column address Y_(i)is input, data DA4 are read from the i-th column onto the read datalines RDB and {overscore (RDB)}. This is followed by a write access thatreplaces data DA4 with data DA9, then a further access to a differentcolumn Y_(i)″.

[0220] Meanwhile, when the cache hit was first recognized, a refreshaddress was generated and the corresponding word line (e.g. WL3) wasactivated in the memory cell array 2. After control line SWa isdeactivated to disconnect the sense lines Si and {overscore (S)}i fromthe column data lines CDi and {overscore (CD)}i, the sense lines Si and{overscore (S)}i and sense amplifiers 16 are equalized, then controlline TG is activated to turn on the transfer circuit 8, coupling thesense lines Si and {overscore (S)}i to the bit lines BLi and {overscore(BL)}i, so that the sense amplifiers can amplify and refresh the data(e.g. DA11) in the memory cells 4 coupled to word line WL3. When theamplification is complete, control line TG is deactivated and the memorycell array 2 is precharged, leaving refreshed data in these memory cells4.

[0221] After control line TG is deactivated, the sense lines Si and{overscore (S)}i are equalized again, then control line SWa is activatedto recouple the sense lines Si and {overscore (S)}i to the column datalines CDi and {overscore (CD)}i. This enables the sense amplifiers toamplify the data DA9 on the column data lines CDi and {overscore (CD)}i,and the subsequently written data DA10.

[0222] Compared with the refresh cycle in FIG. 16, the one in FIG. 19 isfinished earlier, because word line WL3 can be activated at thebeginning of the cache hit cycle, without waiting for the memory cellarray 2 to be precharged.

[0223] From FIGS. 18 and 19, the write buffers 300 can be seen toprovide the following advantages.

[0224] First, every cycle begins with the memory cell array alreadyprecharged. Accordingly, when the memory cell array must be accessed toread or refresh data, the required word line can be activatedimmediately. Access times and cycle times can accordingly be shortened.

[0225] Second, the cycle time in a cache hit can be further shortened,and operating current reduced, by leaving the memory cell array 2disconnected throughout the cycle. No word lines need be activated, andno precharging need be carried out.

[0226] Third, when data are transferred from the memory cell array 2 tothe sense lines, cycle times can be shortened and power dissipationgreatly reduced by turning off the transfer circuit 8 beforeamplification of the data is completed, so that the potential swing onthe bit lines BLi and {overscore (BL)}i remains small.

[0227]FIG. 20 is a circuit diagram showing a transfer control circuitfor controlling the transfer circuit 8.

[0228] In this transfer control circuit, a control circuit 310 receives,among other input signals, the sense amplifier enable signal SAE, andgenerates two control signals T₀ and T₁. Signal T₀ controls the transfercircuit 8 in operations in which data must be transferred from the senselines to the bit lines; these operations include copy-back and refresh.Signal T₁ controls the transfer circuit 8 in operations in which dataare transferred unidirectionally from the bit lines to the sense lines;that is, operations in which it is not necessary to transfer amplifieddata back to the bit lines. In the present DRAM, these can becharacterized as operations in which data are transferred from thememory cell array 2 to the cache.

[0229] A logic circuit 312 combines SAE with T₁ to generate a signal T₂that is active when T₁ is active and SAE is inactive, and is inactive atother times. In FIG. 20 this logic circuit 312 comprises an inverter 314that inverts SAE, and an AND gate 316 that takes the logical AND of T₁and the output of the inverter 314.

[0230] A copy-back detector 318 detects copy-back and refresh operationsand controls a switch 320 that outputs the TG signal that controls thetransfer circuit 8. One input to the switch 320 is T₀. The other inputis the output T₂ of the logic circuit 312; that is, the output of theAND gate 316.

[0231] When the copy-back detector 318 does not detect a copy-back orrefresh operation, it sets the switch 320 as shown in the drawing.Accordingly, after signals T₁, T₂, and TG are activated to turn on thetransfer circuit 8, as soon as SAE goes high and the sense amplifiersare enabled, T₂ and TG are deactivated again by the inverted SAE signal,thereby minimizing amplification of the potential difference on the bitlines.

[0232] When the copy-back detector 318 detects either a copy-back or arefresh, it sets the switch 320 to the opposite position, so that TG isidentical to T₀, and is not deactivated when the sense amplifiers areenabled.

[0233]FIG. 21 illustrates a refresh control circuit that can be used inthe DRAM in FIG. 17. The purpose of this circuit is to combine refreshand copy-back operations.

[0234] In this refresh control circuit, a multiplexer 410 selects eithera row address X indicating data to be accessed or a refresh addressX_(f) indicating data to be refreshed, and supplies the selected addressto the tag circuit 28.

[0235] Part of this refresh control circuit is disposed in the DRAM'scentral control circuit 420, which comprises logic circuits and varioustiming generators that direct operations of the entire DRAM. One ofthese timing generators is a refresh timing generator 421 that generatesa refresh signal REF and two different sets of refresh timing signalsRT1 and RT2. Refresh timing signals RT1 are adapted to control thetype-1 refresh cycle shown in FIG. 19. Refresh timing signals RT2 areadapted for a type-2 refresh cycle, which will be described below.

[0236] The signals REF, RT1, and RT2 are supplied to a refresh selectioncircuit 430, which also receives the cache control signals SWcj (j=1, .. . , n) from the tag circuit 28. The refresh signal REF and cachecontrol signals SWcj are supplied to a logic circuit 431 comprising ann-input OR gate 432 that receives the cache control signals SWcj, and atwo-input AND gate 433 that receives REF and the output of the OR gate432. The output signal C of the AND gate 433 controls a switch 434 thatselects either RT1 or RT2 for supply to circuits (not shown) that directexecution of the type-1 and type-2 refresh cycles.

[0237]FIG. 21 is somewhat simplified; for example, it does not showadditional circuits for distinguishing between a type-1 refresh thatcoincides with a cache hit cycle and a refresh cycle that does notcoincide with a cache hit.

[0238] Next, the operation of the refresh control circuit will bedescribed.

[0239] When a refresh address X_(f) is generated, it is fed through themultiplexer 410 to the tag circuit 28. At the same time, the refreshtiming generator 421 begins generating both sets of refresh timingsignals RT1 and RT2 and activates the refresh signal REF.

[0240] If the refresh address X_(f) does not match the row address heldin any tag memory, the outputs of the OR and AND gates 432 and 433 inthe logic circuit 431 are both low, the switch 432 selects refreshtiming signals RT1, and a type-1 refresh operation is carried out asalready described. If the refresh address X_(f) matches the address inone of the tag circuits, however, the outputs of the OR and AND gates432 and 433 in the logic circuit are both high, the switch 432 selectsthe second set of refresh timing signals RT2, and a type-2 refresh iscarried out as described below. Here it will be assumed that the refreshaddress X_(f) matches row address X₀, which is held in the tag memory 29₁ for cache row 210 ₁.

[0241] Referring again to FIG. 19, in a type-2 refresh operation, theword line WL0 of the memory cells to be refreshed is activated, and thedata DA6 held in the corresponding cache row 210 ₁ are transferred tothe sense lines Si and {overscore (S)}i and amplified by the senseamplifiers 16. This incidentally refreshes the cache row 210 ₁. Afteramplification is complete, control line TG is activated and the transfercircuit 8 is turned on, transferring the data DA8 to the bit lines BLiand {overscore (BL)}i. That is, a copy-back is performed.

[0242] The type-2 refresh in FIG. 19 coincides with a cache hit cycle onrow address X₁, corresponding to cache row 210 ₂. Accordingly, afterdata DA6 have been transferred from the internal column data lines CDiand {overscore (CD)}i to the sense lines Si and {overscore (S)}i,control signal SWa is deactivated to disconnect the column data linesCDi and {overscore (CD)}i from the sense lines Si and {overscore (S)}i,cache control line SWc1 is deactivated, the column data lines CDi and{overscore (CD)}i are equalized, then cache control line SWc2 isactivated, and data DA9 in cache row 210 ₂ are placed on the column datalines CDi and {overscore (CD)}i.

[0243] Subsequent operations in a type-2 refresh are similar to a type-1refresh. Read and write accesses can be carried out on the data on thecolumn data lines CDi and {overscore (CD)}i; in FIG. 19, data DA9 areread from the i-th column, then data DA10 are written in the i-thcolumn. At the end of the cycle, control line TG is deactivated, thetransfer circuit 8 is turned off, the memory cell array 2 is precharged,control line SWa is activated again, and the sense amplifiers 16 areused to amplify the data on the column data lines CDi and {overscore(CD)}i.

[0244] Use of the type-2 refresh cycle has the following advantage.Since data stored in the cache cells 12 _(ij) are not kept up to date inthe memory cell array 2, the cache cells 12 _(ij) must be refreshed toprevent data loss. The refresh control circuit in FIG. 21 assures thatthis will take place. When a refresh address X_(f) is generated, if thecorresponding row of data is not currently stored in the cache, thememory cells 4 are refreshed, e.g. by a type-1 refresh. If thecorresponding row of data is currently stored in the cache, a type-2refresh is carried out, the cache cells are refreshed, and the data arealso copied back to the memory cell array.

[0245] As a result, the cache cells do not have to be designed totolerate longer intervals between refreshes than do the memory cells.Nor is it necessary to increase the refresh rate to provide additionalrefreshes for the cache cells.

[0246] A further advantage occurs if the DRAM remains in standby modefor an extended time. Refreshing continues in standby under control ofthe central control circuit 420, with type-2 refreshes being carried outon data stored in the cache. After all row addresses have beenrefreshed, all data in the cache cells will have been copied back to thememory cells. At this point further refreshing of the cache cells isunnecessary. The tag circuit 28 can now be reset by flagging all cacherows as empty, and current can be conserved by deactivating control lineSWa, so that the column data lines CDi and {overscore (CD)}i do not haveto be charged and discharged.

[0247] To reduce standby current dissipation, the memory cells 4 arepreferably designed to tolerate a relatively slow refresh rate in thestandby state. Another advantage of the refresh control circuit of FIG.21 is that the cache cells do not have to be designed for this slowrefresh rate. Refresh cycles can be executed at a faster rate while theDRAM is active, and until all row addresses have been refreshed once instandby; then the refresh rate can be reduced. The cache design can thusbe simplified: for example, instead of setting the NMOS transistorsubstrate well potential to a negative value, it can be set at groundlevel (Vss), and the substrate well can be shared with the senseamplifiers 16 and other elements, thereby reducing dimensions.

[0248] In addition, the size of the switching transistors in the cachecells can be reduced, so less power is required to drive them.Significant power can be saved in this way, because to enable a Vccpotential to be stored in the cache cells, the cache control linesSWc1-SWcn are driven at an active level higher than Vcc.

[0249] To enable a Vcc potential to be stored in the memory cells, theword lines and transfer gate lines (e.g. TG) must also be driven at anactive level higher than Vcc. With the scheme illustrated in FIGS. 17 to19, however, when data are transferred from the memory cell array to thecache, it is not necessary to drive the word lines and transfer gateline TG at this higher level, because the transfer circuit 8 is turnedoff before amplification of the data is completed. Power can accordinglybe saved by providing three-level drivers for the word lines and TG.

[0250]FIG. 22 illustrates one example of a three-level driver circuitthat can be used for driving the word lines and TG in the DRAM of FIG.17.

[0251] This driver circuit has an input terminal 450 that inputs, forexample, a decoded row address signal to activate a word line, or acontrol signal to activate the TG control line. A copy-back detector 451outputs a copy-back mode signal CBM that is active (high) when acopy-back or refresh is performed. The input signal from input terminal450 and the CBM signal are combined by AND gates 452 and 453 andinverters 454 and 455 to control switches 456, 457, 458, and 459. Switch456 is coupled to a source of a first (boosted) potential V₁ such as Vcc+V_(tn). Switch 456 is coupled to a source of a second potential V₂ suchas Vcc. Both switches 456 and 457 are coupled to an output terminal 460,which is connected to a word line or to control line TG. Switches 458and 459 are coupled in series between the output terminal 460 and ground(Vss).

[0252] This driver circuit operates as follows.

[0253] When the copy-back detector 451 detects a copy-back or refreshoperation, it activates the CBM signal, so that the output of AND gate452 is high or low according to the level of input terminal 450, whilethe output of AND gate 453 is low. Accordingly, signal {overscore (IN)}₂in FIG. 22 is low while {overscore (IN)}₂ is high, and switch 457 is offwhile switch 459 is on. If the input terminal 450 is high, signal IN₁will be high and {overscore (IN)}₁ will be low, switch 456 will be onand switch 458 will be off, and potential V₁ will be coupled to theoutput terminal 460. If the input terminal 450 is low, signal IN₁ willbe low and {overscore (IN)}₁ will be high, switch 456 will be off andswitch 458 will be on, and the output terminal 460 will be coupled toground.

[0254] When the copy-back detector 451 does not detect a copy-back orrefresh, CBM is deactivated (low), making the output of AND gate 452 lowwhile the output of AND gate 453 depends on the logic level of the inputterminal 450. Operations analogous to the above cause the outputterminal 460 to go to V₂ when the input level is high, and to groundwhen the input level is low.

[0255] If this driver is used, then the word lines and TG line will bedriven at a level V₁ higher than Vcc only when a copy-back or refresh iscarried out. At other times they will be driven at the lower V₂ level,thereby conserving power.

[0256]FIG. 23 shows one preferred arrangement of cache cells, switchingelements, and signal lines in the column switching circuit 200 _(i) ofFIG. 14 or 17.

[0257] In this column switching circuit 200 _(i), cache cells 12_(i1)-12 _(i4) are formed in a cache element area 480. To the right ofthis area 480 are to be found read data line {overscore (RDB)}, writedata line {overscore (WDB)}, and the NMOS transistors 219, 221, 223, and226 by which the column data lines CDi and {overscore (CD)}i areinterfaced to these data lines {overscore (RDB)} and {overscore (WDB)}and sense line Si. To the left of this area 480 are to be found readdata line RDB, write data line WDB, and the NMOS transistors 220, 222,224, and 225 by which the column data lines CDi and {overscore (CD)}iare interfaced to RDB, WDB, and sense line {overscore (S)}i. The writecolumn line RCLi and read column line WCLi extend across the area 480,being routed between the column data lines CDi and {overscore (CD)}i.

[0258] This arrangement is symmetrical and permits a dense layout ofsignal lines and circuit elements, regardless of the dimensions of thecircuit elements. It is suitable for high levels of integration.

[0259]FIG. 24 shows another preferred layout. Write data lines{overscore (WDB)} and {overscore (WDB)} are now disposed to the left ofthe cache element area 480, together with the transistors 225 and 226that couple them to the column data lines CDi and {overscore (CD)}i.Read data lines RDB and {overscore (RDB)} are disposed to the right ofthe cache element area 480, together with the transistors 219, 220, 221,and 222 that couple them to the column data lines CDi and {overscore(CD)}i, and transistors 223 and 224 that couple the column data linesCDi and {overscore (CD)}i to the sense lines Si and {overscore (S)}i.

[0260] This layout is also suited for high integration. It furthermoreprevents interference between the read and write data lines, and byplacing complementary bus lines side-by-side, provides good noiseimmunity.

[0261]FIG. 25 shows a layout in which one row 501 of sense amplifiersand column switching circuits is disposed on the left of the memory cellarray 2, and another similar row 502 is disposed on the right of thesame the memory cell array 2. Pairs of complementary bit lines arecoupled alternately to the left row 501 and right row 502. The circuitarea 600 occupied by one sense amplifier and one column switchingcircuit accordingly corresponds to a span 503 of four bit lines, asindicated.

[0262]FIG. 26 shows this circuit area 600 in detail. As in FIGS. 23 and24, cache cells 12 _(i1)-12 _(i4) are disposed between column data linesCDi and {overscore (CD)}i, which are disposed between sense lines Si and{overscore (S)}i. In addition, dummy cells 610 _(i1)-610 _(i4) aredisposed in the cache element area 480 between the column data lines CDiand {overscore (CD)}i and sense lines Si and {overscore (S)}i.

[0263] Each of the cache cells 12 _(i1)-12 _(i4) comprises a switchingelement and a storage element, as in FIG. 2 for example, the switchingelement coupling the storage element to one of the column data lines CDior {overscore (CD)}i. The dummy cells 610 _(i1)-610 _(i4) comprisesimilar switching elements 612 and storage elements 614, with the samedimensions and shapes as the corresponding elements in the cache cells12 _(i1)-12 _(i4), but the switching elements 612 are coupled only tothe storage elements 614, and are not electrically coupled to the columndata lines CDi and {overscore (CD)}i or sense lines Si and {overscore(S)}i.

[0264] For example, if the switching elements 612 in the dummy cells 610_(i1)-610 _(i4) are NMOS transistors, their drains may be coupled to thestorage elements 614, and their sources to the sources of theNMOS-transistor switching elements 612 in the adjacent dummy cells, withno contact holes for coupling the source lines to anything else. Exceptfor this lack of contact holes for the dummy cells 610 _(i1)-610 _(i4),the structure and pitch of the cache cells 12 _(i1)-12 _(i4) and dummycells 610 _(i1)-610 _(i4) closely mimics the structure and pitch of thememory cells in the memory cell array 2. It therefore becomes easy toset fine-pattern fabrication conditions, and production yields can beimproved.

[0265]FIGS. 23, 24, and 26 show only four cache cells 12 _(i1)-12 _(i4)and dummy cells 610 _(i1)-610 _(i4), but of course this is not arestriction; there may be an arbitrary number of each. To simplify FIG.26, the data bus 21 is indicated by a single line DB, and thetransistors that interface the data bus 21 to the column data lines areshown collected into a single block 620, but this should be understoodas representing the arrangement in FIG. 23 or 24, or another suitablearrangement.

[0266] The present invention is not restricted to the above embodiments.For example, the NAND gates in FIGS. 1 and 5 may be replaced bycircuits, similar to the one in FIG. 21, that refresh the cache when thecorresponding rows of memory cells are refreshed. The circuitconfigurations in FIGS. 11, 20, 21, and 22 may be altered in variousways, signal polarities may be reversed, and other modifications whichwill be apparent to those skilled in the art can be made withoutdeparting from the scope of the invention as claimed below. Moreover,many aspects of the invention apply not only to DRAM devices but toother monolithic semiconductor memory devices that can usefully employ abuilt-in cache.

What is claimed is:
 1. A semiconductor memory device, comprising: amemory cell array for storing rows of data having row addresses; a cachefor temporarily storing at least one row of data having an arbitrary rowaddress from among said row addresses; a plurality of sense amplifierscoupled to said memory cell array and said cache, for amplifying datastored in said memory cell array at a first rate, and amplifying datastored in said cache at a second rate faster than said first rate; and adata bus coupled to said sense amplifiers and said cache, for input andoutput of data.
 2. The semiconductor memory device of claim 1 ,comprising a tag circuit coupled to said cache, for storing rowaddresses of the data stored in said cache.
 3. The semiconductor memorydevice of claim 1 , wherein said semiconductor memory device is adynamic random-access memory, requiring periodic refreshing of datastored in said memory cell array, and said cache stores first datahaving one row address while said sense amplifiers refresh second datahaving another address by amplifying said second data in said memorycell array.
 4. The semiconductor memory device of claim 1 , furthercomprising switching elements for disconnecting said cache and said databus from said sense amplifiers, wherein said semiconductor memory deviceis a dynamic random-access memory, requiring periodic refreshing of datastored in said memory cell array, and said sense amplifiers amplify andthereby refresh first data stored in said memory cell array while seconddata are transferred between said cache and said data bus.
 5. Thesemiconductor memory device of claim 1 , comprising write bufferscoupled to said sense amplifiers, for receiving first data stored insaid cache, storing said first data while said first data are replacedin said cache by second data from said memory cell array, andtransferring said first data to said memory cell array after said firstdata have been thus replaced.
 6. A semiconductor memory device,comprising: a rectangular array of memory cells disposed in intersectingrows and columns, for storing data; a plurality of bit lines extendingparallel to said columns and coupled to the memory cells in respectivecolumns, for transporting data to and from said memory cells; aplurality of word lines extending parallel to said rows and coupled tothe memory cells in respective rows, for controlling transfer of databetween said memory cells and said bit lines; a row of first switchingelements coupled to respective bit lines; a plurality of sense linescoupled to respective first switching elements, for transferring datavia said first switching elements to and from said bit lines; a row ofsense amplifiers coupled to said of sense lines, for amplifying data onsaid sense lines; a row of second switching elements coupled torespective sense lines; a data bus for input and output of data; aplurality of column data lines coupled to respective second switchingelements, for interfacing said sense lines to said data bus; a cachehaving at least one row of cache cells coupled to said column datalines, for storing data transferred from an arbitrary row of said memorycells; and a tag circuit coupled to said cache, for storing, for eachsaid row of cache cells, a row address indicating which row of saidmemory cells has data stored in said row of cache cells, and controllingtransfer of data between said row of cache cells and said column datalines responsive to said row address.
 7. The memory device of claim 6 ,wherein: said bit lines are grouped into complementary pairs, with onecomplementary pair of bit lines per column; said sense lines are groupedinto corresponding complementary pairs; and said column data lines aregrouped into corresponding complementary pairs.
 8. The memory device ofclaim 7 , wherein each of said cache cells comprises: a third switchingelement coupled to one of said column data lines and switched on and offby said tag circuit; and a storage element coupled to said switchingelement.
 9. The memory device of claim 8 , wherein: said third switchingelement is a transistor; and said storage element is a capacitor havingone electrode coupled to said transistor and another electrode coupledto a fixed potential.
 10. The memory device of claim 7 , wherein each ofsaid cache cells comprises: a third switching element coupled to one ofsaid column data lines and switched on and off by said tag circuit; afourth switching element coupled to another one of said column datalines and switched on and off by said tag circuit; and a storage elementcoupled in series between said third switching element and said fourthswitching element.
 11. The memory device of claim 7 , wherein each ofsaid sense amplifiers is supplied with two different fixed potentialsfor use in amplifying data on said complementary pairs of sense lines,further comprising: sense-line equalizing circuits coupled to respectivecomplementary pairs of sense lines, for equalizing said sense lines to athird potential intermediate between said two different fixedpotentials; a sense-amplifier equalizing circuit coupled to said row ofsense amplifiers, for supplying said sense amplifiers with said thirdpotential in place of said two different fixed potentials; and a delaycircuit coupled to said sense-amplifier equalizing circuit, for delayingsupply of said third potential to said sense amplifiers until a certaintime after equalization of said sense lines has begun.
 12. The memorydevice of claim 11 , also comprising a hit/miss detector coupled to saiddelay circuit, for preventing the supply of said third potential to saidsense amplifiers prior to transfer of data from said cache cells to saidsense lines.
 13. The memory device of claim 12 , wherein said hit/missdetector comprises: a hit detector for detecting, from an output of saidtag circuit, access to said cache cells, and generating a first signal;a miss detector for detecting, from an output of said tag circuit,access to said memory cells, and generating a second signal thatactivates said sense-amplifier equalizing circuit via said delaycircuit; and a logic gate for combining said first signal and saidsecond signal to produce a third signal, which activates said sense-lineequalizing circuits both when access to said cache cells is detected andwhen access to said memory cells is detected.
 14. The memory device ofclaim 7 , further comprising a row of write buffers coupled betweenrespective complementary pairs of sense lines, for storing data to becopied back from said cache cells to said memory cell array, while otherdata are transferred from said memory cell array to said cache cells.15. The memory device of claim 14 , wherein each of said write bufferscomprises a switching element, a storage element, and another switchingelement coupled in series between a complementary pair of said senselines.
 16. The memory device of claim 14 , comprising a transfer controlcircuit for turning off said first switching elements after data havebeen transferred from said bit lines to said sense lines, but beforesaid sense amplifiers have finished amplifying said data.
 17. The memorydevice of claim 16 , wherein said transfer control circuit comprises: acontrol circuit for generating a first transfer signal for controllingsaid first switching elements when data are transferred unidirectionallyfrom said bit lines to said sense lines; a logic circuit for receivingsaid first transfer signal, also receiving a sense amplifier enablesignal that enables and disables said sense amplifiers, and generating asecond transfer signal that is active if and only if said first transfersignal is active and said sense amplifier enable signal is inactive,said second transfer signal being used to control said first switchingelements.
 18. The memory device of claim 6 , wherein said memory cellsare dynamic memory cells that are refreshed periodically by said senseamplifiers, comprising a refresh control circuit coupled to said tagcircuit, for determining whether data for a row of memory cells to berefreshed are stored in said cache, and if so, refreshing said row ofmemory cells by transferring data from said cache to said row of memorycells.
 19. The memory device of claim 18 , wherein said refresh controlcircuit generates: a first set of refresh timing signals that turn saidfirst switching elements on and said second switching elements off,thereby permitting data in said memory cells to be refreshed by saidsense amplifiers while data are transferred between said column datalines and said data bus; and a second set of refresh timing signals thatturn on both said first switching elements and said second switchingelements, and cause data to be transferred from said cache to said senselines, amplified by said sense amplifiers, then transferred via said bitlines to said memory cells.
 20. The memory device of claim 19 , whereinsaid refresh control circuit comprises: a refresh timing generator forgenerating said first set of refresh timing signals and said second setof refresh timing signals; a multiplexer coupled to said tag circuit,for providing a refresh address to said tag circuit; a logic circuitcoupled to said tag circuit, for deciding whether said refresh addressmatches a row address of data stored in said cache; and a switch coupledto and controlled by said logic circuit, for selecting one set ofrefresh timing signals generated by said refresh timing generator. 21.The memory device of claim 6 , comprising three-level driver circuitsfor driving said word lines and said first switching elements at a firstactive level to transfer data from said sense lines to said memorycells, and at a second active level lower than said first active levelto transfer data from said memory cells via said sense lines to saidcache cells.
 22. The memory device of claim 7 , wherein: said cachecells are disposed in a cache element area; and the second switchingelements coupled to each complementary pair of sense lines are disposedon opposite sides of said cache element area.
 23. The memory device ofclaim 22 , wherein said data bus comprises a complementary pair readdata lines disposed on respective opposite sides of said cache elementarea, and a complementary pair of write data lines also disposed onrespective opposite sides of said cache element area.
 24. The memorydevice of claim 7 , wherein: said cache cells are disposed in a cacheelement area; and both of the second switching elements coupled to eachcomplementary pair of sense lines are disposed on one side of said cacheelement area.
 25. The memory device of claim 24 , wherein said data buscomprises a complementary pair of read data lines both disposed on oneside of said cache element area, and a complementary pair of write datalines both disposed on another side of said cache element area.
 26. Thememory device of claim 7 , wherein: said cache cells are disposed in acache element area; said cache element area also has dummy cells whichare not coupled to said column data lines and are not coupled to saidsense lines; and in their combined arrangement, said cache cells andsaid dummy cells match row and column pitches of said memory cells insaid memory cell array.
 27. The memory device of claim 26 , wherein:each complementary pair of said column data lines is disposed between acomplementary pair of said sense lines; said cache cells are disposedbetween complementary column data lines; and said dummy cells aredisposed between said column data lines and said sense lines.
 28. Asemiconductor memory device, comprising: a rectangular array of memorycells disposed in intersecting rows and columns, for storing data; aplurality of bit lines extending parallel to said columns and coupled tothe memory cells in respective columns, for transporting data to andfrom said memory cells; a plurality of word lines extending parallel tosaid rows and coupled to the memory cells in respective rows, forcontrolling transfer of data between said memory cells and said bitlines; a row of first switching elements coupled to respective bitlines; a plurality of sense lines coupled to respective first switchingelements, for transferring data via said first switching elements to andfrom said bit lines; a row of sense amplifiers coupled to said senselines, for amplifying the data on said sense lines; a row of cache cellscoupled to said sense lines, for storing data of an arbitrary row ofsaid memory cells; and a tag circuit coupled to said row of cache cells,for storing a row address indicating the row of said memory cells havingdata stored in said cache cells, and controlling transfer of databetween said cache cells and said sense lines responsive to said rowaddress.
 29. The memory device of claim 28 , comprising: a plurality ofrows of cache cells as described in claim 31 , for storing data of anarbitrary plurality of rows of said memory cells.
 30. The memory deviceof claim 29 , wherein said tag circuit comprises a plurality of tagmemories for storing row addresses of data stored in corresponding rowsof cache cells.
 31. The memory device of claim 29 , wherein: said memorycell array is divided into left and right banks; said sense lines areswitchably coupled to both said left and right banks; and any row ofcache cells in said plurality of rows of cache cells can store data ofeither of said left and right banks.
 32. The memory device of claim 28 ,wherein: said bit lines are grouped into complementary pairs, with onecomplementary pair of bit lines per column; and said sense lines aregrouped into corresponding complementary pairs.
 33. The memory device ofclaim 32 , wherein each of said cache cells comprises: a secondswitching element coupled to one of said sense lines and switched on andoff by said tag circuit; and a storage element coupled to said secondswitching element.
 34. The memory device of claim 33 , wherein: saidsecond switching element is a transistor; and said storage element is acapacitor having one electrode coupled to said transistor and anotherelectrode coupled to a fixed potential.
 35. The memory device of claim32 , wherein each of said cache cells comprises: a second switchingelement coupled to one of said sense lines and switched on and off bysaid tag circuit; a third switching element coupled to another one ofsaid sense lines and switched on and off by said tag circuit; and astorage element coupled in series between said second switching elementand said third switching element.
 36. The memory device of claim 28 ,wherein: said memory cells are dynamic memory cells that are refreshedperiodically by said sense amplifiers; and said tag circuit preventstransfer of data between said cache cells and said sense lines whilesaid sense amplifiers are refreshing said memory cells.
 37. The memorydevice of claim 32 , wherein each of said sense amplifiers is suppliedwith two different fixed potentials for use in amplifying data on saidcomplementary pairs of sense lines, further comprising: sense-lineequalizing circuits coupled to respective complementary pairs of senselines, for equalizing said sense lines to a third potential intermediatebetween said two different fixed potentials; a sense-amplifierequalizing circuit coupled to said row of sense amplifiers, forsupplying said sense amplifiers with said third potential in place ofsaid two different fixed potentials; and a delay circuit coupled to saidsense-amplifier equalizing circuit, for delaying supply of said thirdpotential to said sense amplifiers until a certain time afterequalization of said sense lines has begun.
 38. The memory device ofclaim 37 , also comprising a hit/miss detector coupled to saidsense-amplifier equalizing circuit, for preventing the supply of saidthird potential to said sense amplifiers prior to transfer of data fromsaid cache cells to said sense lines.
 39. The memory device of claim 38, wherein said hit/miss detector comprises: a hit detector fordetecting, from an output of said tag circuit, access to said cachecells, and generating a first signal; a miss detector for detecting,from an output of said tag circuit, access to said memory cells, andgenerating a second signal that activates said sense-amplifierequalizing circuit via said delay circuit; and a logic gate forcombining said first signal and said second signal to produce a thirdsignal, which activates said sense-line equalizing circuits both whenaccess to said cache cells is detected and when access to said memorycells is detected.
 40. In a semiconductor memory device having wordlines, rows of memory cells coupled to respective word lines, senselines, sense amplifiers coupled to said sense lines, cache cells coupledto said sense lines, and a data bus, a method of executing a memoryaccess cycle, comprising the steps of: receiving a row addressdesignating a row of memory cells; determining if data of said row ofmemory cells are currently present in said sense amplifiers and saidcache cells; transferring said data from said cache cells to said senselines, if said data are currently present in said cache cells but not insaid sense amplifiers, and amplifying the data thus transferred;transferring said data from said memory cells to said sense lines, ifsaid data are currently present in neither said cache cells nor saidsense amplifiers, and amplifying the data thus transferred; receiving atleast one column address and transferring data between correspondingsense lines and said data bus, thereby completing said memory cycle; andleaving said sense amplifiers enabled when said memory cycle ends, sothat said sense amplifiers continue to hold amplified data of the row ofmemory cells designated by said row address.
 41. The method of claim 40, comprising the further steps of: activating a word line correspondingto said row address; transferring amplified data from said sense linesto the memory cells coupled to said word line; and leaving said wordline active when said memory cycle ends.
 42. The method of claim 40 ,wherein the step of transferring data from said memory cells to saidsense lines comprises the further steps of: disabling said senseamplifiers; interconnecting pairs of said sense lines; waiting a certaintime, thus allowing charge on said sense lines to discharge into saidsense amplifiers; then supplying a fixed potential to said sense linesand said sense amplifiers.
 43. The method of claim 40 , wherein the stepof transferring data from said cache cells to said sense lines comprisesthe further steps of: disabling said sense amplifiers; interconnectingpairs of said sense lines; waiting a certain time, thus allowing chargeon said sense lines to discharge into said sense amplifiers; thensupplying a fixed potential to said sense lines but not to said senseamplifiers.
 44. In a semiconductor memory device having word lines, rowsof memory cells coupled to respective word lines, sense lines, senseamplifiers coupled to said sense lines, column data lines coupled tosaid sense lines, cache cells coupled to said column data lines, and adata bus, a method of refreshing said memory cells, comprising the stepsof: receiving a row address corresponding to data stored in said cachecells; transferring said data from said cache cells via said column datalines to said sense lines, and amplifying the data thus transferred;disconnecting said column data lines from said sense lines, therebyleaving amplified data on said column data lines; activating a firstword line; using said sense amplifiers to refresh the memory cellscoupled to said first word line; and receiving at least one columnaddress and transferring data between corresponding column data linesand said data bus, while said sense amplifiers are refreshing saidmemory cells.
 45. The method of claim 44 , comprising the further stepsof: disabling said sense amplifiers after said memory cells have beenrefreshed; coupling said column data lines to said sense lines again;and enabling said sense amplifiers, thereby again amplifying the data onsaid column data lines.
 46. The method of claim 45 , comprising thefurther steps of: deactivating said first word line after said memorycells have been refreshed; activating a second word line correspondingto said row address; and transferring data from said column data linesvia said sense lines to the memory cells coupled to said second wordline.
 47. In a semiconductor memory device having word lines, bit lines,memory cells coupled to said word lines and bit lines, sense lines,sense amplifiers coupled to said sense lines, write buffers coupled tosaid sense lines, column data lines coupled to said sense lines, cachecells coupled to said column data lines, and a data bus, a method ofexecuting a cache load cycle, comprising the steps of: receiving a rowaddress not corresponding to data stored in any of said cache cells;coupling said bit lines to said sense lines; activating a word linecorresponding to said row address; transferring data from memory cellscoupled to said word line via said bit lines to said sense lines;amplifying the data on said sense lines; coupling said column data linesto said sense lines; transferring the data on said sense lines via saidcolumn data lines to said cache cells; and receiving at least one columnaddress and transferring data between said column data lines and saiddata bus, thereby completing said memory cycle.
 48. The method of claim47 , wherein said sense amplifiers are left enabled and when said cacheload cycle ends.
 49. The method of claim 47 , comprising the furthersteps of: disconnecting said bit lines from said sense lines beforeamplification of the data on said sense lines is completed; deactivatingsaid word line; and precharging said bit lines to a fixed potential. 50.The method of claim 47 , wherein the step of transferring data from saidmemory cells to said sense lines comprises the further steps of:disabling said sense amplifiers; interconnecting pairs of said senselines; waiting a certain time, thus allowing charge on said sense linesto discharge into said sense amplifiers; then supplying a fixedpotential to said sense lines and said sense amplifiers.
 51. In asemiconductor memory device having word lines, bit lines, memory cellscoupled to said word lines and bit lines, sense lines, sense amplifierscoupled to said sense lines, write buffers coupled to said sense lines,column data lines coupled to said sense lines, cache cells coupled tosaid column data lines, and a data bus, a method of executing a cachehit cycle, comprising the steps of: receiving a row addresscorresponding to data stored in said cache cells; transferring data fromsaid cache cells via said column data lines to said sense lines;amplifying the data on said sense lines and said column data lines; andreceiving at least one column address and transferring data between saidcolumn data lines and a data bus, thereby completing said cache hitcycle.
 52. The method of claim 51 , wherein said sense amplifiers areleft enabled and when said cache hit cycle ends.
 53. The method of claim51 , wherein said bit lines are left disconnected from said sense linesthroughout said cache hit cycle, and data are not transferred to saidmemory cells.
 54. The method of claim 51 , wherein the step oftransferring data from said cache cells to said sense lines comprisesthe further steps of: disabling said sense amplifiers; interconnectingpairs of said sense lines; waiting a certain time, thus allowing chargeon said sense lines to discharge into said sense amplifiers; thensupplying a fixed potential to said sense lines but not to said senseamplifiers.
 55. In a semiconductor memory device having word lines, bitlines, memory cells coupled to said word lines and bit lines, senselines, sense amplifiers coupled to said sense lines, write bufferscoupled to said sense lines, column data lines coupled to said senselines, at least one row of cache cells coupled to respective column datalines, and a data bus, a method of executing a cache replace cycle,comprising the steps of: receiving a row address not corresponding todata not stored in any of said cache cells; selecting a row of cachecells; transferring data from said row of cache cells to said writebuffers, with amplification by said sense amplifiers; transferring datafrom said memory cells via said sense lines to said column data linesand said row of cache cells, with amplification by said senseamplifiers; disconnecting said column data lines from said sense lines;receiving at least one column address and transferring data betweencorresponding column data lines and said data bus; and transferring datafrom said write buffers to said memory cells, with amplification by saidsense amplifiers.
 56. The method of claim 55 , wherein transferring databetween said column data lines and said data bus and transferring datafrom said write buffers to said memory cells are carried outconcurrently.
 57. The method of claim 55 , comprising the further stepsof: coupling said column data lines to said sense lines, aftertransferring said data from said write buffers to said memory cells; andamplifying the data on said column data lines again.
 58. The method ofclaim 55 , wherein said sense amplifiers are left enabled when saidcache replace cycle ends.
 59. The method of claim 55 , wherein the stepof transferring data from said memory cells comprises: coupling said bitlines to said sense lines; activating a first word line corresponding tosaid row address, thereby transferring said data from the memory cellscoupled to said first word line to said sense lines; and disconnectingsaid bit lines from said sense lines when said data have beentransferred to said sense lines, before amplification of said data iscompleted.
 60. The method of claim 59 , comprising the further steps of:deactivating said first word line; precharging said bit lines to a fixedpotential; activating a second word line corresponding to the datatransferred from said row of cache cells to said write buffer;deactivating said second word line after data have been transferred fromsaid write buffer to the memory cells coupled to said second word line;and precharging said bit lines to said fixed potential again.
 61. In asemiconductor memory device having word lines, bit lines, memory cellscoupled to said word lines and bit lines, sense lines, sense amplifierscoupled to said sense lines, column data lines coupled to said senselines, cache cells coupled to said column data lines, and a data bus, amethod of refreshing said memory cells, comprising the steps of:obtaining a refresh address; determining whether said refresh addresscorresponds to data stored in said cache cells; transferring data fromsaid cache cells via said column data lines, said sense lines, and saidbit lines to said memory cells, with amplification by said senseamplifiers, if said refresh address corresponds to data stored in saidcache cells; and disconnecting said column data lines from said senselines and using said sense amplifiers to refresh said memory cells, ifsaid refresh address does not correspond to data stored in said cachecells.
 62. The method of claim 61 , wherein said cache cells areorganized into at least two rows of cache cells, and the step oftransferring data from said cache cells comprises: selecting a first rowof cache cells corresponding to said refresh address; transferring datafrom said first row of cache cells to said column data lines;transferring data from said column data lines to said sense lines;amplifying the data on said sense lines; disconnecting said column datalines from said sense lines; transferring data from said sense lines tosaid bit lines; receiving a row address corresponding to a second row ofcache cells different from said first row of cache cells; transferringdata from said second row of cache cells to said column data lines; andreceiving at least one column address and transferring data betweencorresponding column data lines and said data bus.
 63. The method ofclaim 62 , wherein transferring data from said second row of cache cellsto said column data lines and transferring data between said column datalines and said data bus are carried out concurrently.
 64. The method ofclaim 61 , comprising the further steps of: coupling said column datalines to said sense lines after said memory cells have been refreshed;transferring data from said column data lines to said sense lines; andamplifying the data on said column data lines and said sense lines.